公开(公告)号：US12238921B2

公开(公告)日：2025-02-25

申请号：US18541566

申请日：2023-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hoon Han ,  Je Min Park

IPC: H10B12/00

Abstract: A semiconductor memory device comprises a substrate, first and second lower electrode groups on the substrate and including a plurality of first and second lower electrodes, respectively, and first and second support patterns on side walls of and connecting each of the first and second lower electrodes, respectively. The first lower electrodes include a first center lower electrode arranged within a hexagonal shape defined by first edge lower electrodes. The second lower electrodes include a second center lower electrode arranged within a hexagonal shape defined by second edge lower electrodes. The first center lower electrode is spaced apart from each of the first edge lower electrodes in different first to third directions. The first support pattern is immediately adjacent to the second support pattern. The first center lower electrode is spaced apart from the second center lower electrode in a fourth direction different from the first to third directions.

公开(公告)号：US11355349B2

公开(公告)日：2022-06-07

申请号：US17032356

申请日：2020-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min Park ,  Se Myeong Jang ,  Bong Soo Kim ,  Je Min Park

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/762

Abstract: A method includes forming hard mask patterns by depositing a support mask layer, a polycrystalline silicon layer, and a hard mask layer on a substrate and etching the hard mask layer, forming pre-polycrystalline silicon patterns by etching the polycrystalline silicon layer using the hard mask patterns as an etch mask, oxidizing side surfaces of the pre-polycrystalline silicon patterns to form polycrystalline silicon patterns and a silicon oxide layer, forming spacer patterns covering sides of the silicon oxide layer, forming a sacrificial layer on a top surface of the support mask layer to cover the silicon oxide layer and the spacer patterns, etching the sacrificial layer and the silicon oxide layer, forming support mask patterns by etching the support mask layer using the polycrystalline silicon patterns and the spacer patterns as an etch mask, and forming activation pins by etching the substrate using the support mask patterns as an etch mask.

公开(公告)号：US10998324B2

公开(公告)日：2021-05-04

申请号：US16890456

申请日：2020-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Wook Jung ,  Dong Oh Kim ,  Seok Han Park ,  Chan Sic Yoon ,  Ki Seok Lee ,  Ho In Lee ,  Ju Yeon Jang ,  Je Min Park ,  Jin Woo Hong

IPC: H01L27/11 ,  H01L27/092 ,  H01L27/108 ,  H01L29/10 ,  H01L21/8238 ,  H01L23/535

Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

公开(公告)号：US10332894B2

公开(公告)日：2019-06-25

申请号：US15828934

申请日：2017-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Wook Jung ,  Dong Oh Kim ,  Seok Han Park ,  Chan Sic Yoon ,  Ki Seok Lee ,  Ho In Lee ,  Ju Yeon Jang ,  Je Min Park ,  Jin Woo Hong

IPC: H01L27/11 ,  H01L29/10 ,  H01L27/108 ,  H01L21/8238 ,  H01L27/092

Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

公开(公告)号：US10141316B2

公开(公告)日：2018-11-27

申请号：US15275827

申请日：2016-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Seok Lee ,  Jeong Seop Shim ,  Mi Na Lee ,  Augustin Jinwoo Hong ,  Je Min Park ,  Hye Jin Seong ,  Seung Min Oh ,  Do Yeong Lee ,  Ji Seung Lee ,  Jin Seong Lee

IPC: H01L27/108

Abstract: A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.