公开(公告)号：US20130259489A1

公开(公告)日：2013-10-03

申请号：US13834991

申请日：2013-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jangseok CHOI ,  Soo-Jeong LEE

IPC: G06F13/38

CPC classification number: G06F13/38 ,  G06F13/385

Abstract: A memory expanding device for expanding a main memory of an external device connected to the memory expanding device through an optical interface.

Abstract translation: 一种存储器扩展装置，用于通过光接口扩展连接到存储器扩展装置的外部设备的主存储器。

公开(公告)号：US20240143173A1

公开(公告)日：2024-05-02

申请号：US18408558

申请日：2024-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien CHANG ,  Dimin NIU ,  Hongzhong ZHENG ,  Sun Young LIM ,  Indong KIM ,  Jangseok CHOI

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/106 ,  G11C29/52 ,  G11C5/04

Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

公开(公告)号：US20200167297A1

公开(公告)日：2020-05-28

申请号：US16777206

申请日：2020-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dimin NIU ,  Mu-Tien CHANG ,  Hongzhong ZHENG ,  Sun Young LIM ,  lndong KIM ,  Jangseok CHOI ,  Craig HANSON

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: A memory module includes: a non-volatile memory; and an asynchronous memory interface to interface with a memory controller. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.

公开(公告)号：US20190266049A1

公开(公告)日：2019-08-29

申请号：US16411122

申请日：2019-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin NIU ,  Mu-Tien CHANG ,  Hongzhong ZHENG ,  Hyun-Joong KIM ,  Won-Hyung SONG ,  Jangseok CHOI

IPC: G06F11/10 ,  G11C29/52 ,  G11C11/4093

Abstract: A data chip that may pollute data is disclosed. The data chip may include a data array, read circuitry to read raw data from the data array, and a buffer to store the raw data. Using a pollution pattern stored in a mask register, a data pollution engine may pollute the raw data. Transmission circuitry may then transmit the polluted data.

公开(公告)号：US20170365305A1

公开(公告)日：2017-12-21

申请号：US15231629

申请日：2016-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mu-Tien CHANG ,  Dimin NIU ,  Hongzhong ZHENG ,  Craig HANSON ,  Sun Young LIM ,  Indong KIM ,  Jangseok CHOI

IPC: G11C7/10 ,  G06F1/32

CPC classification number: G11C7/1072 ,  G06F1/32 ,  G06F1/3234 ,  G06F1/325 ,  G06F1/3275 ,  G06F1/3287 ,  G11C5/04 ,  G11C5/148 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4074 ,  G11C2207/2227 ,  Y02D10/14 ,  Y02D50/20

Abstract: A memory module includes a plurality of memory components, an in-memory power manager, and an interface to a host computer over a memory bus. The in-memory power manager is configured to control a transition of a power state of the memory module. The transition of the power state of the memory module includes a direct transition from a low power down state to a maximum power down state.