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11.
公开(公告)号:US11768656B2
公开(公告)日:2023-09-26
申请号:US17248861
申请日:2021-02-10
Applicant: Samsung Electronics Co., Ltd.
Inventor: Wookwang Lee , Kyounghoon Kim , Hyungsik Park , Dongrak Shin , Youngjung Yoon , Jaejin Lee
CPC classification number: G06F3/162 , G06F3/165 , G06F13/4282 , H04R3/00 , G06F2213/0042 , H04R2420/05 , H04R2420/09
Abstract: Embodiments of an electronic device are disclosed. The electronic device may include a USB Type-C connector including at least one configuration channel (CC) pin and a processor operatively connected to the USB Type-C connector. The processor may be configured to: obtain first information of a connected audio output device by using a USB driver; transmit the first information and/or audio card information of the audio output device to an audio framework through a USB framework; control the audio framework to access an interface corresponding to the audio card information; and activate, when at least a portion of second information of the audio output device is obtained through the USB driver while accessing the interface, the interface by transmitting the at least a portion of the second information to the audio framework through the USB framework. Various additional embodiments in addition to the disclosed embodiments are possible.
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公开(公告)号:USD954368S1
公开(公告)日:2022-06-07
申请号:US29750889
申请日:2020-09-17
Applicant: Samsung Electronics Co., Ltd.
Designer: Jinsook Park , Jaejin Lee , Sodam Park , Sanghoon Yoon , Deoksang Yun
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公开(公告)号:US10347527B2
公开(公告)日:2019-07-09
申请号:US15975003
申请日:2018-05-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sangho Rha , Kyoung Hee Nam , Jeonggil Lee , Hyunseok Lim , Seungjong Park , Seulgi Bae , Jaejin Lee , Kwangtae Hwang
IPC: H01L21/768 , H01L23/532
Abstract: A semiconductor device includes a substrate, a first metal interconnection provided on a first region of the substrate, and a second metal interconnection provided on a second region of the substrate. A width of the second metal interconnection is greater than a width of the first metal interconnection. The first metal interconnection includes a metal pattern. The second metal interconnection includes a lower metal pattern having a concave surface at its top, an upper metal pattern disposed on the concave surface at the top of the lower metal pattern, and a first barrier pattern interposed between the lower metal pattern and the upper metal pattern. The metal interconnections are formed by a damascene process including deposition, reflow, metal implantation, and planarization processes.
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14.
公开(公告)号:US12204812B2
公开(公告)日:2025-01-21
申请号:US18243431
申请日:2023-09-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: Wookwang Lee , Kyounghoon Kim , Hyungsik Park , Dongrak Shin , Youngjung Yoon , Jaejin Lee
Abstract: Embodiments of an electronic device are disclosed. The electronic device may include a USB Type-C connector including at least one configuration channel (CC) pin and a processor operatively connected to the USB Type-C connector. The processor may be configured to: obtain first information of a connected audio output device by using a USB driver; transmit the first information and/or audio card information of the audio output device to an audio framework through a USB framework; control the audio framework to access an interface corresponding to the audio card information; and activate, when at least a portion of second information of the audio output device is obtained through the USB driver while accessing the interface, the interface by transmitting the at least a portion of the second information to the audio framework through the USB framework. Various additional embodiments in addition to the disclosed embodiments are possible.
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公开(公告)号:US20230063527A1
公开(公告)日:2023-03-02
申请号:US17747238
申请日:2022-05-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jaejin Lee , Youngjun Kim , Hunyoung Bark , Taekyung Yoon , Eunok Lee
IPC: H01L29/49 , H01L27/108
Abstract: A gate structure includes a first gate electrode including a metal, a gate barrier pattern on the first gate electrode and including a metal nitride, and a second gate electrode on the gate barrier pattern. The gate structure is buried in an upper portion of a substrate. The gate barrier pattern has a flat upper surface and an uneven lower surface.
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公开(公告)号:US11359856B2
公开(公告)日:2022-06-14
申请号:US16876685
申请日:2020-05-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Chanbin Park , Yang-Yeol Gu , Jaejin Lee , Jeonghyun Lee
Abstract: A refrigerator with an enhanced door includes a main body including a storeroom, first and second doors pivotally coupled to the main body to open or close the storeroom and a pivot bar pivotally installed at the first door. The pivot bar is movable between a first position between the first and second doors and a second position pivoted toward the first door to prevent cold air leaks from the storeroom. A locking device separably locks the pivot bar to the first door when the pivot bar is in the second position.
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公开(公告)号:USD937507S1
公开(公告)日:2021-11-30
申请号:US29769805
申请日:2021-02-08
Applicant: Samsung Electronics Co., Ltd.
Designer: Jaejin Lee , Jinsook Park
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公开(公告)号:USD917804S1
公开(公告)日:2021-04-27
申请号:US29724639
申请日:2020-02-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Designer: Jinsook Park , Sodam Park , Jaejin Lee , Deoksang Yun
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公开(公告)号:USD854764S1
公开(公告)日:2019-07-23
申请号:US29622050
申请日:2017-10-13
Applicant: Samsung Electronics Co., Ltd.
Designer: Yuna Park , Sanghun Yoon , Jaejin Lee
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公开(公告)号:US09997400B2
公开(公告)日:2018-06-12
申请号:US15332297
申请日:2016-10-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sangho Rha , Kyoung Hee Nam , Jeonggil Lee , Hyunseok Lim , Seungjong Park , Seulgi Bae , Jaejin Lee , Kwangtae Hwang
IPC: H01L21/768
CPC classification number: H01L21/76816 , H01L21/7684 , H01L21/76847 , H01L21/76849 , H01L21/76864 , H01L21/76867 , H01L21/76882 , H01L23/53238
Abstract: A semiconductor device includes a substrate, a first metal interconnection provided on a first region of the substrate, and a second metal interconnection provided on a second region of the substrate. A width of the second metal interconnection is greater than a width of the first metal interconnection. The first metal interconnection includes a metal pattern. The second metal interconnection includes a lower metal pattern having a concave surface at its top, an upper metal pattern disposed on the concave surface at the top of the lower metal pattern, and a first barrier pattern interposed between the lower metal pattern and the upper metal pattern. The metal interconnections are formed by a damascene process including deposition, reflow, metal implantation, and planarization processes.
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