公开(公告)号：US10692565B2

公开(公告)日：2020-06-23

申请号：US16707738

申请日：2019-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Wook Kim ,  Hyuk-Joon Kwon ,  Sang-Keun Han ,  Bok-Yeon Won

IPC: G11C11/4091 ,  G11C7/06 ,  G11C11/4097 ,  G11C11/4094 ,  G11C7/02 ,  G11C5/02 ,  G11C11/4096 ,  G11C5/06 ,  G11C11/408

Abstract: A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

公开(公告)号：US10262935B2

公开(公告)日：2019-04-16

申请号：US15677054

申请日：2017-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Ju Kim ,  Su-A Kim ,  Soo-Young Kim ,  Min-Woo Won ,  Bok-Yeon Won ,  Ji-Suk Kwon ,  Young-Ho Kim ,  Ji-Hak Yu ,  Hyun-Chul Yoon ,  Seok-Jae Lee ,  Sang-Keun Han ,  Woong-Dai Kang ,  Hyuk-Joon Kwon ,  Bum-Jae Lee

IPC: H01L23/522 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4097 ,  H01L23/528 ,  H01L23/00 ,  H01L23/50 ,  H01L23/552 ,  G11C7/10 ,  G11C7/06

Abstract: A memory device including a memory cell array region, includes, column selection signal lines formed in a first column conduction layer of the memory cell array region and extending in a column direction, global input-output data lines formed in a second column conduction layer of the memory cell array region different from the first column conduction layer and extending in the column direction and power lines formed in a shield conduction layer of the memory cell array region between the first column conduction layer and the second column conduction layer. The noises in the signal lines and the power lines may be reduced and performance of the memory device may be enhanced by forming the column selection signal lines and the global input-output data lines in different column conduction layers and forming the power lines in the shield conduction layer between the column conduction layers.

公开(公告)号：US10224093B2

公开(公告)日：2019-03-05

申请号：US15697164

申请日：2017-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Wook Kim ,  Hyuk-Joon Kwon ,  Sang-Keun Han ,  Bok-Yeon Won

IPC: G11C5/06 ,  G11C5/02 ,  G11C7/06 ,  G11C11/4091 ,  G11C7/02 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/4096 ,  G11C11/408

Abstract: A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

公开(公告)号：US09768129B2

公开(公告)日：2017-09-19

申请号：US15200523

申请日：2016-07-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Seob Lee ,  Hyuk-Joon Kwon ,  Bo-Tak Lim

IPC: H01L23/48 ,  H01L23/58 ,  H01L21/66 ,  H01L23/00 ,  H01L29/49 ,  H01L23/528

CPC classification number: H01L23/573 ,  G01R31/2884 ,  H01L22/34 ,  H01L23/522 ,  H01L23/5283 ,  H01L23/585 ,  H01L29/4916 ,  H01L2224/0401 ,  H01L2924/1434

Abstract: A semiconductor device includes a semiconductor die, a semiconductor integrated circuit and a three-dimensional crack detection structure. The semiconductor die includes a central region and a peripheral region surrounding the central region. The semiconductor integrated circuit is formed in the central region. The three-dimensional crack detection structure is formed in a ring shape in the peripheral region to surround the central region. The three-dimensional crack detection structure is expanded in a vertical direction. Using the three-dimensional crack detection structure, the crack penetration of various types may be detected thoroughly.