公开(公告)号：US20250157523A1

公开(公告)日：2025-05-15

申请号：US19024300

申请日：2025-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiheung Kim ,  Taeyoung Oh ,  Jongcheol Kim ,  Kyungho Lee ,  Hyongryol Hwang

IPC: G11C11/4078 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a control logic circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data based on an active command applied to the control logic circuit at a first time point, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row in response to a precharge command applied at a second time point after a first command that is applied to the control logic circuit.

公开(公告)号：US20250149077A1

公开(公告)日：2025-05-08

申请号：US18937774

申请日：2024-11-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Yoon ,  Jaemin Choi ,  ChangSik Yoo ,  Ki-Heung Kim ,  Hoseok Seol ,  Youngdo Um ,  Hyongryol Hwang

IPC: G11C8/18 ,  G11C8/06 ,  H03K19/173 ,  H03K21/08

Abstract: An input/output interface circuit includes a common receiving driver configured to receive a differential clock signal and output a first clock signal corresponding to the differential clock signal and a pair of sub-channels connected to the common receiving driver. Each sub-channel of the pair of sub-channels may be configured to receive the first clock signal and a chip select signal, output a second clock signal through a logical AND operation of the first clock signal and the chip select signal, and output a single clock signal, among the second clock signal and one or more divided clock signals. The single clock signal is used to sample a command address signal.

公开(公告)号：US12236997B2

公开(公告)日：2025-02-25

申请号：US18357204

申请日：2023-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiheung Kim ,  Taeyoung Oh ,  Jongcheol Kim ,  Kyungho Lee ,  Hyongryol Hwang

IPC: G11C11/4078 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a control logic circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data based on an active command applied to the control logic circuit at a first time point, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row in response to a precharge command applied at a second time point after a first command that is applied to the control logic circuit.

公开(公告)号：US20240345944A1

公开(公告)日：2024-10-17

申请号：US18634559

申请日：2024-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KI-HEUNG KIM ,  Taeyoung Oh ,  Taekwoon Kim ,  Jinseong Yun ,  Yoonjae Jeong ,  Hyongryol Hwang

IPC: G06F12/02

CPC classification number: G06F12/0223 ,  G06F2212/202

Abstract: A method of operating a memory configured to communicate with a memory controller, the method includes: temporarily storing a unique identification (ID) for each of a plurality of memory devices included in the memory to each of the plurality of memory devices; selecting a target memory device from among the plurality of memory devices; and permanently or substantially permanently programming, in the target memory device, a unique ID corresponding to the target memory device.

公开(公告)号：US20230420033A1

公开(公告)日：2023-12-28

申请号：US18196703

申请日：2023-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongcheol Kim ,  Kiheung Kim ,  Taeyoung Oh ,  Kyungho Lee ,  Hyongryol Hwang

IPC: G11C11/4078 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4094

CPC classification number: G11C11/4078 ,  G11C11/4087 ,  G11C11/4096 ,  G11C11/4094

Abstract: A semiconductor memory device, including a memory cell array; a row hammer management circuit configured to: count a number of accesses based on an active command, and based on a first command applied after the active command, perform an internal read-update-write operation to read the count data from the count cells of a target memory cell row, and to write updated count data in the count cells of the target memory cell row; and a column decoder configured to: access a first memory cell using a first bit-line; and store data in the first memory cell using a first voltage, or perform an internal write operation to store the count data in the first memory cell using a second voltage greater than the first voltage during an internal write time interval smaller than a reference write time interval.

公开(公告)号：US20250078906A1

公开(公告)日：2025-03-06

申请号：US18818007

申请日：2024-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-Heung Kim ,  ChangSik Yoo ,  Jeongdon Ihm ,  Hyongryol Hwang

IPC: G11C11/408 ,  G11C11/4093 ,  G11C11/4096

Abstract: A memory device includes a bank array including a plurality of memory cells, a row decoder connected to the bank array through a plurality of wordlines, and a column decoder connected to the bank array through a plurality of column select lines. The bank array may include a first region and a second region different from the first region. First metadata for first normal data stored in the first region is stored in the second region, and second metadata for second normal data stored in the second region is stored in the first region.

公开(公告)号：US12175099B2

公开(公告)日：2024-12-24

申请号：US18302276

申请日：2023-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungho Lee ,  Kiheung Kim ,  Taeyoung Oh ,  Jongcheol Kim ,  Hyongryol Hwang

IPC: G06F3/06

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows and a row hammer management circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row. The row hammer management circuit includes a hammer address queue. The row hammer management circuit changes the updated count data randomly, based on an event signal indicating a state change of the hammer address queue.

公开(公告)号：US20240404584A1

公开(公告)日：2024-12-05

申请号：US18678401

申请日：2024-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-Heung Kim ,  Taeyoung Oh ,  Jongcheol Kim ,  Kyung-Ho Lee ,  Hyongryol Hwang

IPC: G11C11/4096 ,  G11C11/4076 ,  G11C11/4093

Abstract: An example memory device includes a memory cell array, a row hammer management circuit, and a read-modify-write (RMW) driver. The memory cell array includes a plurality of memory cell rows and stores count data for a number of accesses to each memory cell row. The row hammer management circuit performs an RMW operation that reads out count data corresponding to a target memory cell row among the memory cell rows, updates the read-out count data, and writes the updated count data in the memory cell array. The RMW driver generates control signals to control the RMW operation based on a precharge command. The target memory cell row is precharged after a predetermined time is elapsed from a time point where the precharge command is applied.

公开(公告)号：US20230410925A1

公开(公告)日：2023-12-21

申请号：US18239548

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minho Choi ,  Jaeseong Lim ,  Kyungryun Kim ,  Daehyun Kim ,  Wonil Bae ,  Hohyun Shin ,  Sanghoon Jung ,  Hyongryol Hwang

IPC: G11C17/18 ,  G11C29/08 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C17/16 ,  G11C29/08

Abstract: A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.

公开(公告)号：US20220284975A1

公开(公告)日：2022-09-08

申请号：US17591987

申请日：2022-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minho Choi ,  Jaeseong Lim ,  Kyungryun Kim ,  Daehyun Kim ,  Wonil Bae ,  Hohyun Shin ,  Sanghoon Jung ,  Hyongryol Hwang

IPC: G11C17/18 ,  G11C17/16 ,  G11C29/08

Abstract: A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.