公开(公告)号：US20210157672A1

公开(公告)日：2021-05-27

申请号：US16891517

申请日：2020-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changkyu SEOL ,  Hyejeong SO ,  Kwanwoo NOH ,  Hongrak SON ,  Pilsang YOON

IPC: G06F11/10 ,  H03M13/13

Abstract: Channel selection information indicate positions of data bits of input data, positions of error correction code (ECC) parity bits for correcting errors in the input data, and positions of state shaping parity bits. The ECC parity bits and the state shaping parity bits are generated to cause a decrease in a quantity of memory cells, of the plurality of memory cells, in which at least one target state among a plurality of states is programmed. An alignment vector is generated based on aligning the data bits of the input data, the ECC parity bits, and the state shaping parity bits, based on the channel selection information. A codeword is generated based on simultaneously performing state shaping and ECC encoding with respect to the alignment vector. Write data are written in the nonvolatile memory device based on the codeword.

公开(公告)号：US20230269067A1

公开(公告)日：2023-08-24

申请号：US17968375

申请日：2022-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongrak SON ,  Sangpyo KIM ,  Jongmin KIM ,  Jungho AHN ,  Hanbyeul NA ,  Youngsik MOON ,  Junho SHIN

IPC: H04L9/00 ,  H04L9/06 ,  G06F7/72

CPC classification number: H04L9/008 ,  G06F7/722 ,  H04L9/0618 ,  H04L2209/122

Abstract: A method of operating a homomorphic encryption operation accelerator includes performing a number theoretic transform (NTT) operation on each of first homomorphic ciphertext and second homomorphic ciphertext, and performing a base conversion operation by adding a partial sum using a first value of the NTT operation.

公开(公告)号：US20230146149A1

公开(公告)日：2023-05-11

申请号：US17739512

申请日：2022-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngsik MOON ,  Jiyoup KIM ,  Hanbyeul NA ,  Hongrak SON

IPC: H04L9/00 ,  H04L9/06

CPC classification number: H04L9/008 ,  H04L9/0618

Abstract: A homomorphic encryption system includes a homomorphic encryption device encrypting original data into a first ciphertext using a homomorphic encryption algorithm, and a homomorphic encryption operation device receiving the first ciphertext from the homomorphic encryption device and performing an approximate arithmetic operation of a transcendental function with respect to the first ciphertext and a second ciphertext by performing a homomorphic multiplication operation in a binary tree structure.

公开(公告)号：US20230065578A1

公开(公告)日：2023-03-02

申请号：US17847744

申请日：2022-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjun HWANG ,  Hongrak SON ,  Geunyeong YU

IPC: G11C29/52 ,  G11C29/02 ,  G11C7/10 ,  G11C7/22

Abstract: Various example embodiments of the inventive concepts provide an error correction circuit and a semiconductor device. The error correction circuit includes clock-sync distributor circuitry configured to output a plurality of distributor output data based on distributor reception data received using a first clock signal, each of the plurality of distributor output data output based on the first clock signal or a second clock signal, the second clock signal having a higher frequency than a frequency of the first clock signal, a node processor configured to generate a plurality of output data by performing error correction decoding using the plurality of distributor output data, output a first subset of the plurality of output data based on the first clock signal, and output a second subset of the plurality of output data based on the second clock signal, and clock-sync combiner circuitry configured to output, based on the first clock signal, the plurality of output data received from the node processor.

公开(公告)号：US20220199185A1

公开(公告)日：2022-06-23

申请号：US17392781

申请日：2021-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoon YOON ,  Hyeonjong SONG ,  Seonghyeog CHOI ,  Hongrak SON

IPC: G11C29/42 ,  G11C29/18 ,  G11C16/34

Abstract: In a method of predicting a remaining lifetime of the nonvolatile memory device, a read sequence is performed. The read sequence includes a plurality of read operations, and at least one of the plurality of read operations is sequentially performed until read data stored in the nonvolatile memory device is successfully retrieved. Sequence class and error correction code (ECC) decoding information are generated. A life stage of the nonvolatile memory device is determined based on at least one of the sequence class and the ECC decoding information. When it is determined that the nonvolatile memory device corresponds to a first life stage, a coarse prediction on the remaining lifetime of the nonvolatile memory device is performed. When it is determined that the nonvolatile memory device corresponds to a second life stage after the first life stage, a fine prediction on the remaining lifetime of the nonvolatile memory device is performed.

公开(公告)号：US20210224638A1

公开(公告)日：2021-07-22

申请号：US17002035

申请日：2020-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehun JANG ,  Hongrak SON

IPC: G06N3/063 ,  G06F12/06 ,  G06N3/08 ,  G06N3/04

Abstract: A storage controller includes a learning pattern processor and a storage processor. The learning pattern processor estimates request prediction data to be requested by a host per epoch to generate estimated result values of the request prediction data. The storage processor reads the request prediction data from a storage memory to store the request prediction data in a buffer memory based on the estimated result values before the host issues a read request for the request prediction data. An operation speed of the buffer memory is higher than an operation speed of the storage memory.

公开(公告)号：US20210150321A1

公开(公告)日：2021-05-20

申请号：US16906209

申请日：2020-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehun JANG ,  Hongrak SON ,  Changkyu SEOL ,  Hyejeong SO ,  Hwaseok OH ,  Pilsang YOON ,  Jinsoo LIM

IPC: G06N3/063 ,  G06N3/08 ,  G06F7/544 ,  G06F15/80

Abstract: A storage system includes a host device and a storage device. The host device provides first input data for data storage function and second input data for artificial intelligence (AI) function. The storage device stores the first input data from the host device, and performs AI calculation based on the second input data to generate calculation result data. The storage device includes a first processor, a first nonvolatile memory, a second processor and a second nonvolatile memory. The first processor controls an operation of the storage device. The first nonvolatile memory stores the first input data. The second processor performs the AI calculation, and is distinguished from the first processor. The second nonvolatile memory stores weight data associated with the AI calculation, and is distinguished from the first nonvolatile memory.