公开(公告)号：US20210150321A1

公开(公告)日：2021-05-20

申请号：US16906209

申请日：2020-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehun JANG ,  Hongrak SON ,  Changkyu SEOL ,  Hyejeong SO ,  Hwaseok OH ,  Pilsang YOON ,  Jinsoo LIM

IPC: G06N3/063 ,  G06N3/08 ,  G06F7/544 ,  G06F15/80

Abstract: A storage system includes a host device and a storage device. The host device provides first input data for data storage function and second input data for artificial intelligence (AI) function. The storage device stores the first input data from the host device, and performs AI calculation based on the second input data to generate calculation result data. The storage device includes a first processor, a first nonvolatile memory, a second processor and a second nonvolatile memory. The first processor controls an operation of the storage device. The first nonvolatile memory stores the first input data. The second processor performs the AI calculation, and is distinguished from the first processor. The second nonvolatile memory stores weight data associated with the AI calculation, and is distinguished from the first nonvolatile memory.

公开(公告)号：US20230057630A1

公开(公告)日：2023-02-23

申请号：US17870200

申请日：2022-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongyeon WOO ,  Minje KIM ,  Woongseop LEE ,  Dongjun YU ,  Jinsoo LIM

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

Abstract: A device includes: a stack structure including first and second stack regions; first and second separation structures penetrating the stack structure; and vertical structures penetrating the stack structure, including first and second vertical memory structures spaced from the first separation structure by different lengths. The first and second vertical memory structures each include a lower portion, penetrating the first stack region, and an upper portion penetrating the second stack region. A first distance between a center of an upper region of the upper portion of the first vertical memory structure and a center of an upper region of the upper portion of the second vertical memory structure is different from a second distance between a center of an upper region of the lower portion of the first vertical memory structure and a center of an upper region of the lower portion of the second vertical memory structure.

公开(公告)号：US20210013304A1

公开(公告)日：2021-01-14

申请号：US16701427

申请日：2019-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojoon RYU ,  Kiyoon KANG ,  Seogoo KANG ,  Shinhwan KANG ,  Jesuk MOON ,  Byunggon PARK ,  Jaeryong SIM ,  Jinsoo LIM ,  Jisung CHEON ,  Jeehoon HAN

IPC: H01L29/06 ,  H01L23/31 ,  G11C5/06 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor device including a substrate having a cell, peripheral, and boundary area; a stack structure on the cell area and including insulating and interconnection layers that are alternately stacked; a molding layer on the peripheral area boundary areas; a selection line isolation pattern extending into the stack structure; a cell channel structure passing through the stack structure; and first dummy patterns extending into the molding layer on the peripheral area, wherein upper surfaces of the first dummy patterns, an upper surface of the selection line isolation pattern, and an upper surface of the cell channel structure are coplanar, and at least one of the first dummy patterns extends in parallel with the selection line isolation pattern or cell channel structure from upper surfaces of the first dummy patterns, the upper surface of the selection line isolation pattern, and the upper surface of the cell channel structure toward the substrate.

公开(公告)号：US20220271056A1

公开(公告)日：2022-08-25

申请号：US17744092

申请日：2022-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisung CHEON ,  Byunggon PARK ,  Joowon PARK ,  Sangjun HONG ,  Jinsoo LIM

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/28 ,  H01L23/535

Abstract: An integrated circuit device including a substrate having a cell and interconnection region; and a first stacked structure and a second stacked structure on the first stacked structure, each of the first and second stacked structures including insulating layers and word line structures that are alternately stacked one by one on the substrate in the cell region and the interconnection region, wherein, in the interconnection region the first stacked structure includes a first dummy channel hole penetrating through the first stacked structure, the second stacked structure includes a second dummy channel hole communicatively connected to the first dummy channel hole, the second dummy channel hole penetrating through the second stacked structure, respectively, and a first dummy upper width of an uppermost end of the first dummy channel hole is greater than a second dummy upper width of an uppermost end of the second dummy channel hole.

公开(公告)号：US20210183885A1

公开(公告)日：2021-06-17

申请号：US17025120

申请日：2020-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongyeon WOO ,  Sangjun HONG ,  Jinsoo LIM ,  Jisung CHEON

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11556 ,  G11C8/14

Abstract: A semiconductor device includes: a first gate stack including a plurality of first gate electrodes; a second gate stack arranged on the first gate stack and including a plurality of second gate electrodes; and a plurality of channel structures arranged in a plurality of channel holes penetrating the first gate stack and the second gate stack. Each of the channel holes includes a first channel hole portion penetrating the first gate stack and a second channel hole portion penetrating the second gate stack, and a ratio of a second width in the second direction to a first width in the first direction of an upper end of the first channel hole portion is less than a ratio of a fourth width in the second direction to a third width in the first direction of an upper end of the second channel hole portion.