公开(公告)号：US11586543B2

公开(公告)日：2023-02-21

申请号：US17380805

申请日：2021-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Heehyun Nam ,  Jaeho Shin ,  Hyodeok Shin ,  Younggeon Yoo ,  Younho Jeon ,  Wonseb Jeong ,  Ipoom Jeong ,  Hyeokjun Choe

IPC: G06F12/00 ,  G06F12/0817 ,  G06F3/06 ,  G06F12/0862

Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.

公开(公告)号：US10762000B2

公开(公告)日：2020-09-01

申请号：US15662072

申请日：2017-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Heehyun Nam ,  Youngsik Kim ,  Youngjin Cho ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F12/121 ,  G06F12/127 ,  G06F13/16 ,  G06F12/0868

Abstract: A method of choosing a cache line of a plurality of cache lines of data for eviction from a frontend memory, the method including assigning a baseline replacement score to each way of a plurality of ways of a cache, the ways respectively storing the cache lines, assigning a validity score to each way based on a degree of validity of the cache line stored in each way, assigning an eviction decision score to each way based on a function of the baseline replacement score for the way and the validity score for the way, and choosing a cache line of the way having a highest eviction decision score as the cache line for eviction.

公开(公告)号：US20230205423A1

公开(公告)日：2023-06-29

申请号：US18087464

申请日：2022-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heeyeon TAK ,  Hyunseon Park ,  Heehyun Nam ,  Sumin Ahn ,  Wansoo Choi

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0656 ,  G06F3/0679

Abstract: A memory system includes a memory device including a memory cell array, a first latch, a plurality of program latches, and a second latch and a memory controller configured to provide a command to the memory device. The memory device may sense first data from a first region of the memory cell array, store the sensed first data in the first latch, transfer the sensed first data to the second latch, output the first data from the second latch to the memory controller, and transfer the first data from the second latch to a first program latch of the plurality of program latches, in response to a first read command.

公开(公告)号：US20220147470A1

公开(公告)日：2022-05-12

申请号：US17466726

申请日：2021-09-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho LEE ,  Younho Jeon ,  Daehui Kim ,  Heehyun Nam

IPC: G06F13/16 ,  G06F13/40

Abstract: A device configured to communicate through a bus may include a first interface circuit configured to, based on a first protocol, provide first access to a first memory through the bus and a second interface circuit configured to, based on a second protocol, provide a non-coherent input/output (I/O) interface through the bus. The second interface circuit may be configured to access the first memory in response to a message received through the bus based on the second protocol to provide second access to the first memory through the bus.

公开(公告)号：US11175853B2

公开(公告)日：2021-11-16

申请号：US15669851

申请日：2017-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Heehyun Nam ,  Youngjin Cho ,  Sun-Young Lim

IPC: G06F3/00 ,  G06F12/00 ,  G06F3/06 ,  G06F12/0895 ,  G06F12/0868 ,  G06F13/16 ,  G06F12/02

Abstract: A memory module includes a memory controller including: a host layer; a media layer coupled to a non-volatile memory; and a logic core coupled to the host layer, the media layer, and a volatile memory, the logic core storing a first write group table including a plurality of rows, and the logic core being configured to: receive a persistent write command including a cache line address and a write group identifier; receive data associated with the persistent write command; write the data to the volatile memory at the cache line address; store the cache line address in a selected buffer of a plurality of buffers in a second write group table, the selected buffer corresponding to the write group identifier; and update a row of the first write group table to identify locations of the selected buffer containing valid entries, the row corresponding to the write group identifier.

公开(公告)号：US20180293175A1

公开(公告)日：2018-10-11

申请号：US15662072

申请日：2017-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Heehyun Nam ,  Youngsik Kim ,  Youngjin Cho ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F12/121

Abstract: A method of choosing a cache line of a plurality of cache lines of data for eviction from a frontend memory, the method including assigning a baseline replacement score to each way of a plurality of ways of a cache, the ways respectively storing the cache lines, assigning a validity score to each way based on a degree of validity of the cache line stored in each way, assigning an eviction decision score to each way based on a function of the baseline replacement score for the way and the validity score for the way, and choosing a cache line of the way having a highest eviction decision score as the cache line for eviction.