公开(公告)号：US10403329B2

公开(公告)日：2019-09-03

申请号：US16000399

申请日：2018-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-Jae Han ,  Il-Mok Kang ,  Ki-Woong Yoo ,  In-jae Lee ,  Gwang-man Lim

IPC: G11C5/14 ,  G06K19/077 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  H01R12/73 ,  H01R13/66

Abstract: A memory card and an electronic system including the memory card. The memory card includes: a substrate having two pairs of edges, in which the edges of each pair face each other; a plurality of first row terminals that are arranged adjacent to an edge at an insertion side of the substrate and include a first voltage power terminal; a plurality of second row terminals that are spaced farther apart from the edge at the insertion side than the plurality of first row terminals and include a power terminal of a second voltage. According to the memory card, efficient use of an area may be maximized and an electrically stable power supply may be provided.

公开(公告)号：US10157678B2

公开(公告)日：2018-12-18

申请号：US14824061

申请日：2015-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-jae Han ,  Il-mok Kang ,  Gwang-man Lim ,  Seok-heon Lee ,  Jae-bum Lee

IPC: G11C16/32 ,  G11C16/30 ,  G06K19/077

Abstract: A memory card is provided to include a substrate having two pairs of edges facing each other, a plurality of first row terminals that are arranged adjacent to an edge at an insertion side of the substrate and include a first voltage power terminal for applying a first voltage and a first ground terminal, a plurality of second row terminals that are spaced farther apart from the edge at the insertion side than the plurality of first row terminals and include a second voltage power terminal for applying a second voltage and first data terminals, and a plurality of third row terminals that are spaced farther apart from the edge at the insertion side than the plurality of second row terminals and include second data terminals.

公开(公告)号：US20140225281A1

公开(公告)日：2014-08-14

申请号：US14250934

申请日：2014-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chul Park ,  Hyeong-seob Kim ,  Kun-dae Yeom ,  Gwang-man Lim

IPC: H01L23/535 ,  H01L25/065 ,  H01L23/50

CPC classification number: H01L23/49541 ,  H01L23/49575 ,  H01L23/50 ,  H01L23/535 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01075 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/48175 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Provided is a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are exposed to the outside of the semiconductor package. The plurality of leads may include a first lead group for a first chip group and a second lead group for a second chip group. The first and second chip groups are part of the package.

Abstract translation: 提供了包括多个半导体芯片的半导体封装以及连接到半导体芯片的分离的引线组。 引线暴露于半导体封装的外部。 多个引线可以包括用于第一芯片组的第一引线组和用于第二芯片组的第二引线组。 第一和第二芯片组是封装的一部分。