公开(公告)号：US20240224533A1

公开(公告)日：2024-07-04

申请号：US18605115

申请日：2024-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changsun Hwang ,  Youngjin Kwon ,  Gihwan Kim ,  Hansol Seok ,  Dongseog Eun ,  Jongheun Lim

IPC: H10B43/40 ,  H01L23/522 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: An integrated circuit device includes: a substrate having a cell region, a peripheral circuit region, and an interconnection region between the cell region and the peripheral circuit region; a first cell stack structure and a second cell stack structure on the first cell stack structure, each including a plurality of insulating layers and a plurality of word line structures alternately stacked on the substrate; and a dummy stack structure located at a same vertical level as the second cell stack structure, and including a plurality of dummy insulating layers and a plurality of dummy support layers alternately stacked in the peripheral circuit region.

公开(公告)号：US20240138141A1

公开(公告)日：2024-04-25

申请号：US18402144

申请日：2024-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Giyong Chung ,  Youngjin Kwon ,  Dongseog Eun

IPC: H10B12/00

CPC classification number: H10B12/395 ,  H10B12/0383 ,  H10B12/50

Abstract: A vertical-type nonvolatile memory device has a multi-stack structure with reduced susceptibility to mis-alignment of a vertical channel layer. This nonvolatile memory device includes: (i) a main chip area including a cell area and an extension area arranged to have a stepped structure, with the cell area and the extension area formed in a multi-stack structure, and (ii) an outer chip area, which surrounds the main chip area and includes a step key therein. The main chip area includes a first layer on a substrate and a second layer on the first layer. A lower vertical channel layer is arranged in the first layer. The step key includes an alignment vertical channel layer, and a top surface of the alignment vertical channel layer is lower than a top surface of the lower vertical channel layer.

公开(公告)号：US10741574B2

公开(公告)日：2020-08-11

申请号：US15955256

申请日：2018-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangyoung Jung ,  Jongwon Kim ,  Dongseog Eun ,  Joonhee Lee

IPC: H01L27/11568 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11575

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure including conductive layers stacked on the substrate. Moreover, the semiconductor device includes a dummy structure penetrating a stepped region of the stack structure. A portion of the dummy structure includes a first segment and a second segment. The first segment extends in a first direction in a plane parallel to an upper surface of the substrate. The second segment protrudes from the first segment in a second direction, in the plane, that intersects the first direction.

公开(公告)号：US12219760B2

公开(公告)日：2025-02-04

申请号：US17338823

申请日：2021-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kangmin Kim ,  Seungmin Song ,  Dongseog Eun ,  Seokhwa Jung

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A semiconductor chip includes a substrate, a source structure disposed on the substrate, and a support pattern disposed on the source structure. Each of the source structure and the support pattern includes polysilicon. The semiconductor chip further includes an electrode structure disposed on the support pattern, and a plurality of vertical structures extending vertically through the electrode structure. The electrode structure includes a lower electrode structure disposed on the support pattern and including a plurality of lower gate electrodes and a plurality of first insulating films, a second insulating film disposed on the lower electrode structure, and an upper electrode structure disposed on the second insulating film and including a plurality of upper gate electrodes and a plurality of third insulating films. The vertical structures contact the source structure above the source structure.

公开(公告)号：US11895827B2

公开(公告)日：2024-02-06

申请号：US17469469

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Giyong Chung ,  Youngjin Kwon ,  Dongseog Eun

IPC: H10B12/00

CPC classification number: H10B12/395 ,  H10B12/0383 ,  H10B12/50

Abstract: A vertical-type nonvolatile memory device has a multi-stack structure with reduced susceptibility to mis-alignment of a vertical channel layer. This nonvolatile memory device includes: (i) a main chip area including a cell area and an extension area arranged to have a stepped structure, with the cell area and the extension area formed in a multi-stack structure, and (ii) an outer chip area, which surrounds the main chip area and includes a step key therein. The main chip area includes a first layer on a substrate and a second layer on the first layer. A lower vertical channel layer is arranged in the first layer. The step key includes an alignment vertical channel layer, and a top surface of the alignment vertical channel layer is lower than a top surface of the lower vertical channel layer.

公开(公告)号：US11716844B2

公开(公告)日：2023-08-01

申请号：US16985024

申请日：2020-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjae Lee ,  Jaehyung Kim ,  Dongseog Eun

IPC: H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes an upper stack structure extending on a lower stack structure, which extends on an underlying substrate. A channel structure extends through the upper stack structure and the lower stack structure. The lower stack structure includes a first lower electrode layer disposed adjacent to an interface between the lower stack structure and the upper stack structure, and a second lower electrode layer disposed adjacent a center of the lower stack structure. The upper stack structure includes a first upper electrode layer disposed adjacent to the interface, and a second upper electrode layer disposed adjacent a center of the upper stack structure. At least one of the first lower electrode layer and the first upper electrode layer is thicker than the second lower electrode layer. At least one insulating layer is disposed between the first lower electrode layer and the first upper electrode layer.

公开(公告)号：US20220199626A1

公开(公告)日：2022-06-23

申请号：US17469469

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Giyong Chung ,  Youngjin Kwon ,  Dongseog Eun

IPC: H01L27/108

Abstract: A vertical-type nonvolatile memory device has a multi-stack structure with reduced susceptibility to mis-alignment of a vertical channel layer. This nonvolatile memory device includes: (i) a main chip area including a cell area and an extension area arranged to have a stepped structure, with the cell area and the extension area formed in a multi-stack structure, and (ii) an outer chip area, which surrounds the main chip area and includes a step key therein. The main chip area includes a first layer on a substrate and a second layer on the first layer. A lower vertical channel layer is arranged in the first layer. The step key includes an alignment vertical channel layer, and a top surface of the alignment vertical channel layer is lower than a top surface of the lower vertical channel layer.

公开(公告)号：US20200335520A1

公开(公告)日：2020-10-22

申请号：US16921185

申请日：2020-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangyoung Jung ,  Jongwon Kim ,  Dongseog Eun ,  Joonhee Lee

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11575

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure including conductive layers stacked on the substrate. Moreover, the semiconductor device includes a dummy structure penetrating a stepped region of the stack structure. A portion of the dummy structure includes a first segment and a second segment. The first segment extends in a first direction in a plane parallel to an upper surface of the substrate. The second segment protrudes from the first segment in a second direction, in the plane, that intersects the first direction.