公开(公告)号：US20220254650A1

公开(公告)日：2022-08-11

申请号：US17517304

申请日：2021-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do Young CHOI ,  Sung Min KIM ,  Cheol KIM ,  Hyo Jin KIM ,  Dae Won HA ,  Dong Woo HAN

IPC: H01L21/3213 ,  H01L21/308

Abstract: Provided is a semiconductor device. The semiconductor device comprises a first active pattern extending in a first direction on a substrate, a second active pattern which extends in the first direction and is adjacent to the first active pattern in a second direction different from the first direction, a field insulating film placed between the first active pattern and the second active pattern, a first gate structure which crosses the first active pattern, extends in the second direction, and includes a first gate electrode and a first gate spacer, a second gate structure which crosses the second active pattern, extends in the second direction, and includes a second gate electrode and a second gate spacer, a gate separation structure placed on the field insulating film between the first gate structure and the second gate structure.

公开(公告)号：US20210167184A1

公开(公告)日：2021-06-03

申请号：US17176226

申请日：2021-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guk Il AN ,  Keun Hwi CHO ,  Dae Won HA ,  Seung Seok HA

IPC: H01L29/51 ,  H01L27/088 ,  H01L23/522 ,  H01L49/02 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.

公开(公告)号：US20200294995A1

公开(公告)日：2020-09-17

申请号：US16734786

申请日：2020-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG MIN KIM ,  Dae Won HA

IPC: H01L27/06 ,  H01L27/088 ,  H01L23/528 ,  H01L29/78 ,  H01L29/417

Abstract: A semiconductor device including: a lower semiconductor substrate; an upper semiconductor substrate overlapping the lower semiconductor substrate, the upper semiconductor substrate including a first surface and a second surface opposite to the first surface; an upper gate structure on the first surface of the upper semiconductor substrate; a first interlayer insulation film which covers the upper gate structure, wherein the first interlayer insulation film is between the lower semiconductor substrate and the upper semiconductor substrate; and an upper contact connected to the lower semiconductor substrate, wherein the upper contact is on a side surface of the upper gate structure, wherein the upper contact includes a first portion penetrating the upper semiconductor substrate, and a second portion having a side surface adjacent to the side surface of the upper gate structure, and a width of the first portion decreases toward the second surface.

公开(公告)号：US20200243684A1

公开(公告)日：2020-07-30

申请号：US16848145

申请日：2020-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Gun YOU ,  Dong Hyun KIM ,  Byoung-Gi KIM ,  Yun Suk NAM ,  Yeong Min JEON ,  Sung Chul PARK ,  Dae Won HA

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L23/532 ,  H01L29/06 ,  H01L29/165

Abstract: A semiconductor device includes first and second fin patterns on a substrate and extending apart from each other, a field insulating film on the substrate and surrounding parts of the first and second fin patterns, a first gate structure on the first fin pattern and intersecting the first fin pattern, a second gate structure on the second fin pattern and intersecting the second fin pattern, and a separating structure protruding from a top surface of the field insulating film and separating the first and second gate structures, the field insulating film and the separating structure including a same insulating material.

公开(公告)号：US20240047521A1

公开(公告)日：2024-02-08

申请号：US18488381

申请日：2023-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul SUN ,  Dae Won HA ,  Dong Hoon HWANG ,  Jong Hwa BAEK ,  Jong Min JEON ,  Seung Mo HA ,  Kwang Yong YANG ,  Jae Young PARK ,  Young Su CHUNG

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L27/0886 ,  H01L21/823431 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/41791

Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.

公开(公告)号：US20240014288A1

公开(公告)日：2024-01-11

申请号：US18369450

申请日：2023-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guk Il AN ,  Keun Hwi CHO ,  Dae Won HA ,  Seung Seok HA

IPC: H01L23/522 ,  H01L27/088 ,  H01L23/528 ,  H01L29/417

CPC classification number: H01L23/5223 ,  H01L27/0886 ,  H01L23/5283 ,  H01L29/41791

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.

公开(公告)号：US20230084804A1

公开(公告)日：2023-03-16

申请号：US17833058

申请日：2022-06-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Moon CHOI ,  Sung Il PARK ,  Dae Won HA

IPC: H01L29/417 ,  H01L29/78

Abstract: A semiconductor device is provided. The semiconductor device includes: a first active pattern extending in a first direction; a second active pattern spaced apart extending in the first direction, the first active pattern being provided between the second active pattern and a substrate; a gate structure extending in a second direction, the first active pattern and the second active pattern passing through the gate structure, and the second direction crossing the first direction; a first source/drain area connected with the first active pattern and provided on a side of the gate structure; a second source/drain area connected with the second active pattern and provided on the first source/drain area; a first insulating structure provided between the substrate and the first source/drain area, the first insulating structure not being provided between the substrate and the gate structure; and a second insulating structure provided between the first source/drain area and the second source/drain area.

公开(公告)号：US20220310654A1

公开(公告)日：2022-09-29

申请号：US17502380

申请日：2021-10-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Do Young CHOI ,  Kab Jin NAM ,  In Bong POK ,  Dae Won HA ,  Musarrat HASAN

IPC: H01L27/11592 ,  H01L27/1159 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device, the method including providing a substrate including a first region and a second region such that the second region is separated from the first region; forming a metal oxide film on the first region of the substrate and the second region of the substrate; forming an upper metal material film on the metal oxide film on the first region of the substrate such that the upper metal material film does not overlap the metal oxide film on the second region of the substrate; and simultaneously annealing the upper metal material film and the metal oxide film to form a ferroelectric insulating film on the first region of the substrate and form a paraelectric insulating film on the second region of the substrate.

公开(公告)号：US20220037319A1

公开(公告)日：2022-02-03

申请号：US17210751

申请日：2021-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mun Hyeon KIM ,  Sung Min KIM ,  Dae Won HA

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes a substrate with first and second regions separated from each other, a laminate structure including at least one sacrificial layer and at least one active layer alternately stacked on the substrate, a first isolation insulating layer on the laminate structure on the first region, a second isolation insulating layer on the laminate structure on the second region, the second isolation insulating layer having a same thickness as the first isolation insulating layer, a first upper active pattern spaced apart from the first isolation insulating layer, a first gate electrode surrounding at least a portion of the first upper active pattern, a second upper active pattern spaced apart from the second isolation insulating layer, and a second gate electrode surrounding at least a portion of the second upper active pattern, wherein top surfaces of the first and second isolation insulating layers are at different heights.

公开(公告)号：US20200043928A1

公开(公告)日：2020-02-06

申请号：US16354369

申请日：2019-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo Jin KIM ,  Dae Won HA ,  Yoon Moon PARK ,  Keun Hwi CHO

IPC: H01L27/092

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first transistor including a single first active fin disposed in the first region, a first gate electrode intersecting the single first active fin, and a single first source/drain layer disposed in the first recess of the single first active fin, and a second transistor including a plurality of second active fins disposed in the second region, a second gate electrode intersecting the plurality of second active fins, and a plurality of second source/drain layers disposed in the second recesses of the plurality of second active fins. The single first active fin and the plurality of second active fins may have a first conductivity type, and a depth of the first recess may be less than a depth of each of the second recesses.