公开(公告)号：US20240136266A1

公开(公告)日：2024-04-25

申请号：US18490995

申请日：2023-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin YIM ,  Jiyong PARK

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/3135 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15174 ,  H01L2924/15184

Abstract: A semiconductor package includes a first redistribution structure including a first redistribution layer and a first redistribution bonding pad, the first redistribution bonding pad electrically connected to the first redistribution layer, a first semiconductor chip on the first redistribution structure, and a second redistribution structure on the first semiconductor chip, the second redistribution structure including a second redistribution layer and a second redistribution bonding pad, the second redistribution layer electrically connected to the second redistribution layer. The semiconductor package includes a bonding wire electrically connecting the second redistribution bonding pad and the first redistribution bonding pad to each other, and a molding layer covering at least a portion the first semiconductor chip, the second redistribution structure, and the bonding wire on the first redistribution structure.

公开(公告)号：US20240047418A1

公开(公告)日：2024-02-08

申请号：US18199553

申请日：2023-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin YIM ,  Gitae Park ,  Jinwoo Park

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/49827 ,  H01L25/18 ,  H10B80/00 ,  H01L23/49833 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/16 ,  H01L2924/1435 ,  H01L2924/1431 ,  H01L2924/181 ,  H01L2224/16227

Abstract: A semiconductor package includes: a redistribution layer including a plurality of redistribution patterns; a sub-semiconductor package including a sub-semiconductor package substrate and a first semiconductor chip that is on the sub-semiconductor package substrate, wherein the sub-semiconductor package substrate is on the redistribution layer and includes a plurality of first lower surface pads; and a second semiconductor chip on the redistribution layer and spaced apart from the sub-semiconductor package in a horizontal direction, wherein the second semiconductor chip includes a chip pad, wherein at least some of the plurality of redistribution patterns of the redistribution layer are overlapped with and electrically connected to the plurality of first lower surface pads of the sub-semiconductor package, respectively.

公开(公告)号：US20230021867A1

公开(公告)日：2023-01-26

申请号：US17715417

申请日：2022-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Choongbin YIM ,  Jongbo SHIM ,  Jihwang KIM

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package includes: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate and electrically connected to the lower wiring layer; an upper substrate disposed on the semiconductor chip and including a core layer, an upper wiring layer, a plurality of dummy structures, and a solder resist layer, wherein the core layer has through-holes, wherein the plurality of dummy structures are disposed in the through-holes and are electrically insulated from the upper wiring layer, and wherein the solder resist layer covers the upper wiring layer and extends in the through-holes; a connection structure disposed between the lower substrate and the upper substrate; an encapsulant disposed between the lower substrate and the upper substrate and encapsulating at least a portion of each of the semiconductor chip and the connection structure; and a connection bump disposed on the lower substrate.

公开(公告)号：US20220406766A1

公开(公告)日：2022-12-22

申请号：US17807691

申请日：2022-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choongbin YIM ,  Jinwoo PARK

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56

Abstract: A semiconductor package includes: a package substrate; a semiconductor chip mounted above the package substrate; a chip connection terminal interposed between the semiconductor chip and the package substrate; an adhesive layer disposed on the package substrate and that covers a side and a top surface of the semiconductor chip and surrounds the chip connection terminal between the semiconductor chip and the package substrate; a molding layer disposed on the package substrate and that surrounds the adhesive layer; an interposer mounted on the adhesive layer and the molding layer, where the interposer includes an interposer substrate; and a conductive pillar disposed on the package substrate, where the conductive pillar surrounds the side of the semiconductor substrate, penetrates the molding layer in a vertical direction and connects the package substrate to the interposer substrate.