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公开(公告)号:US10211156B2
公开(公告)日:2019-02-19
申请号:US16119475
申请日:2018-08-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Changseop Yoon , Kwangsub Yoon , Jongmil Youn , Hyung Jong Lee
IPC: H01L23/528 , H01L21/8238 , H01L27/02 , H01L23/485 , H01L29/06
Abstract: A semiconductor device includes a substrate including PMOSFET and NMOSFET regions, a first gate structure extending in a first direction and crossing the PMOSFET and NMOSFET regions, and a gate contact on and connected to the first gate structure, the gate contact being between the PMOSFET and NMOSFET regions, the gate contact including a first sub contact in contact with a top surface of the first gate structure, the first sub contact including a vertical extending portion extending vertically toward the substrate along one sidewall of the first gate structure, and a second sub contact spaced apart from the first gate structure, a top surface of the second sub contact being positioned at a same level as a top surface of the first sub contact.
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公开(公告)号:US10431586B2
公开(公告)日:2019-10-01
申请号:US16244540
申请日:2019-01-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Changseop Yoon , Sungmin Kim , Chiwon Cho
IPC: H01L27/092 , H01L23/485 , H01L29/417 , H01L21/8238 , H01L29/06 , H01L27/11 , H01L27/088 , H01L27/02 , H01L29/66 , H01L29/165 , H01L21/8234
Abstract: A semiconductor device including a first fin active area substantially parallel to a second fin active area, a first source/drain in the first fin active area, a second source/drain in the second fin active area, a first contact plug on the first source/drain, and a second contact plug on the second source/drain. The center of the second contact plug is offset from the center of the second source/drain.
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公开(公告)号:US10109645B2
公开(公告)日:2018-10-23
申请号:US15786864
申请日:2017-10-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Changseop Yoon , Junggun You , YoungJoon Park , Jeonghyo Lee
IPC: H01L21/70 , H01L21/336 , H01L27/118 , H01L29/423 , H01L29/66 , H01L21/762 , H01L29/78 , H01L29/06
Abstract: A semiconductor device includes a first device isolation layer defining active regions spaced apart from each other along a first direction on a substrate, second device isolation layers defining a plurality of active patterns protruding from the substrate, the second device isolation layers extending in the first direction to be spaced apart from each other in a second direction and connected to the first device isolation layer, a gate structure extending in the second direction on the first device isolation layer between the active regions, a top surface of the second device isolation layer being lower than a top surface of the active pattern, a top surface of the first device isolation layer being higher than the top surface of the active pattern, and at least part of a bottom surface of the gate structure being higher than the top surface of the active pattern.
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公开(公告)号:US10096546B2
公开(公告)日:2018-10-09
申请号:US15704049
申请日:2017-09-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Changseop Yoon , Kwangsub Yoon , Jongmil Youn , Hyung Jong Lee
IPC: H01L23/528 , H01L21/8238 , H01L29/06 , H01L27/02 , H01L23/485
Abstract: A semiconductor device includes a substrate including PMOSFET and NMOSFET regions, a first gate structure extending in a first direction and crossing the PMOSFET and NMOSFET regions, and a gate contact on and connected to the first gate structure, the gate contact being between the PMOSFET and NMOSFET regions, the gate contact including a first sub contact in contact with a top surface of the first gate structure, the first sub contact including a vertical extending portion extending vertically toward the substrate along one sidewall of the first gate structure, and a second sub contact spaced apart from the first gate structure, a top surface of the second sub contact being positioned at a same level as a top surface of the first sub contact.
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公开(公告)号:US09799674B2
公开(公告)日:2017-10-24
申请号:US15050607
申请日:2016-02-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Changseop Yoon , Junggun You , YoungJoon Park , Jeonghyo Lee
IPC: H01L21/70 , H01L21/336 , H01L27/118 , H01L29/78 , H01L29/423 , H01L29/66 , H01L29/06 , H01L21/762
CPC classification number: H01L29/7846 , H01L21/76224 , H01L27/11807 , H01L29/0653 , H01L29/0673 , H01L29/4236 , H01L29/42376 , H01L29/66621 , H01L29/66659
Abstract: A semiconductor device includes a first device isolation layer defining active regions spaced apart from each other along a first direction on a substrate, second device isolation layers defining a plurality of active patterns protruding from the substrate, the second device isolation layers extending in the first direction to be spaced apart from each other in a second direction and connected to the first device isolation layer, a gate structure extending in the second direction on the first device isolation layer between the active regions, a top surface of the second device isolation layer being lower than a top surface of the active pattern, a top surface of the first device isolation layer being higher than the top surface of the active pattern, and at least part of a bottom surface of the gate structure being higher than the top surface of the active pattern.
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公开(公告)号:US09748243B2
公开(公告)日:2017-08-29
申请号:US15049721
申请日:2016-02-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Changseop Yoon , Sungmin Kim , Chiwon Cho
IPC: H01L21/70 , H01L27/092 , H01L27/088 , H01L29/66 , H01L29/06 , H01L23/485 , H01L29/165
CPC classification number: H01L27/0924 , H01L21/823431 , H01L21/823475 , H01L21/823821 , H01L21/823871 , H01L23/485 , H01L27/0207 , H01L27/0886 , H01L27/1104 , H01L29/0653 , H01L29/165 , H01L29/41791 , H01L29/665
Abstract: A semiconductor device including a first fin active area substantially parallel to a second fin active area, a first source/drain in the first fin active area, a second source/drain in the second fin active area, a first contact plug on the first source/drain, and a second contact plug on the second source/drain. The center of the second contact plug is offset from the center of the second source/drain.
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