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    Semiconductor device and method of manufacturing the same
    11.
    发明授权
    Semiconductor device and method of manufacturing the same 有权

    公开(公告)号：US10050041B1

    公开(公告)日：2018-08-14

    申请号：US15954744

    申请日：2018-04-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chan-Sic Yoon ,  Ho-In Ryu ,  Ki-Seok Lee ,  Chang-Hyun Cho

    IPC: H01L27/108 ,  H01L29/423 ,  H01L21/761 ,  H01L21/311

    Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation layer and at least a gate trench linearly extending in a first direction to cross the active region, the active region having a gate area at a bottom of the gate trench and a junction area at a surface of the substrate. The device further may include a first conductive line filling the gate trench and extending in the first direction, the first conductive line having a buried gate structure on the gate area of the active region. The device also may include a junction including implanted dopants at the junction area of the active region, and a junction separator on the device isolation layer and defining the junction. The junction separator may be formed of an insulative material and have an etch resistance greater than that of the device isolation layer.

    SEMICONDUCTOR MEMORY DEVICE
    14.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240355362A1

    公开(公告)日：2024-10-24

    申请号：US18503222

    申请日：2023-11-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Han Seong Shin ,  Ki Seok Lee ,  Keun Nam Kim ,  Hui-Jung Kim ,  Chan-Sic Yoon

    IPC: G11C5/06 ,  H10B12/00

    CPC classification number: G11C5/063 ,  H10B12/315 ,  H10B12/482 ,  H10B12/485

    Abstract: A semiconductor memory device includes a substrate comprising an element isolation layer, a bit line that extends on the substrate in a first direction, a cell buffer insulating layer between the bit line and the substrate and comprising an upper cell buffer insulating layer and a lower cell buffer insulating layer, a lower storage contact disposed on a plurality of sides of the bit line and comprising a semiconductor epitaxial pattern, a storage pad on the lower storage contact and connected to the lower storage contact and an information storage unit on the storage pad and connected to the storage pad, wherein the upper cell buffer insulating layer is between the lower cell buffer insulating layer and the bit line, and each of the lower cell buffer insulating layer and the upper cell buffer insulating layer comprises an upper surface and a lower surface that are opposite to each other.

    Semiconductor devices and methods for fabricating the same
    15.
    发明授权
    Semiconductor devices and methods for fabricating the same 有权

    公开(公告)号：US11201156B2

    公开(公告)日：2021-12-14

    申请号：US16934874

    申请日：2020-07-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chan-Sic Yoon ,  Dongoh Kim ,  Kiseok Lee ,  Sunghak Cho ,  Jemin Park

    IPC: H01L27/108 ,  H01L21/762 ,  H01L21/311

    Abstract: A semiconductor device includes a substrate that includes a cell region and a peripheral circuit region, a cell insulating pattern disposed in the cell region of the substrate that defines a cell active region, and a peripheral insulating pattern disposed in the peripheral circuit region of the substrate that defines a peripheral active region. The peripheral insulating pattern includes a first peripheral insulating pattern having a first width and a second peripheral insulating pattern having a second width greater than the first width. A topmost surface of at least one of the first peripheral insulating pattern and the second peripheral insulating pattern is positioned higher than a topmost surface of the cell insulating pattern.

    Semiconductor device including a bit line
    18.
    发明授权
    Semiconductor device including a bit line 有权

    公开(公告)号：US10332831B2

    公开(公告)日：2019-06-25

    申请号：US15638552

    申请日：2017-06-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Augustin Jinwoo Hong ,  Dae-Ik Kim ,  Chan-Sic Yoon ,  Ki-Seok Lee ,  Dong-Min Han ,  Sung-Ho Jang ,  Yoo-Sang Hwang ,  Bong-Soo Kim ,  Je-Min Park

    IPC: H01L27/108 ,  H01L23/522 ,  H01L27/11568 ,  H01L21/768

    Abstract: A semiconductor device includes a substrate including a cell array region including a cell active region. An insulating pattern is on the substrate. The insulating pattern includes a direct contact hole which exposes the cell active region and extends into the cell active region. A direct contact conductive pattern is in the direct contact hole and is connected to the cell active region. A bit line is on the insulating pattern. The bit line is connected to the direct contact conductive pattern and extends in a direction orthogonal to an upper surface of the insulating pattern. The insulating pattern includes a first insulating pattern including a non-metal-based dielectric material and a second insulating pattern on the first insulating pattern. The second insulating pattern includes a metal-based dielectric material having a higher dielectric constant than a dielectric constant of the first insulating pattern.

    Semiconductor devices using auxiliary layers for trimming margin and devices so formed
    19.
    发明授权
    Semiconductor devices using auxiliary layers for trimming margin and devices so formed 有权

    公开(公告)号：US10312105B2

    公开(公告)日：2019-06-04

    申请号：US15598861

    申请日：2017-05-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chan-Sic Yoon ,  Jiung Pak ,  Kiseok Lee ,  Chan Ho Park ,  Hyeonok Jung

    IPC: H01L21/308 ,  H01L27/108

    Abstract: A method of fabricating a semiconductor device includes forming a linear preliminary mask pattern in a first direction on a substrate. The preliminary mask pattern is patterned to provide a plurality of mask patterns that are aligned end-to-end with one another on the substrate and are separated by an exposed portion of the substrate between respective facing ends of the plurality of mask patterns. An auxiliary layer is formed to cover at least sidewalls of the facing ends to reduce a size of the exposed portion to provide a reduced exposed portion of the substrate and the reduced exposed portion of the substrate is etched to form a trench defining active patterns in the substrate aligned end-to-end with one another.

    Semiconductor devices and methods of manufacturing semiconductor devices
    20.
    发明授权
    Semiconductor devices and methods of manufacturing semiconductor devices 有权
    半导体器件和制造半导体器件的方法

    公开(公告)号：US09478548B2

    公开(公告)日：2016-10-25

    申请号：US14639360

    申请日：2015-03-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Do-Yeong Lee ,  Chan-Sic Yoon ,  Ki-Seok Lee ,  Hyeon-Ok Jung

    IPC: H01L27/108 ,  H01L21/8242 ,  H01L29/78 ,  H01L21/28 ,  H01L21/311 ,  H01L21/02 ,  H01L29/423

    CPC classification number: H01L27/10823 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/4236

    Abstract: A method of manufacturing a semiconductor device includes forming an isolation pattern on a substrate to define active patterns each having a first contact region at a center portion thereof and second and third contact regions at edge portions thereof. The method further includes forming a buried gate structure at upper portions of the isolation pattern and the active patterns, forming a first insulation layer on the isolation pattern and the active patterns, and etching a portion of the first insulation layer and an upper portion of the first contact region to form a preliminary opening exposing the first contact region. The method still further includes etching the isolation pattern to form an opening, forming an insulation pattern on a sidewall of the opening, and forming a wiring structure contacting the first contact region in the opening.

    Abstract translation: 一种制造半导体器件的方法包括在衬底上形成隔离图案以限定其中心部分具有第一接触区域和其边缘部分处的第二和第三接触区域的有源图案。 该方法还包括在隔离图案的上部形成掩埋栅极结构和有源图案，在隔离图案和有源图案上形成第一绝缘层，并蚀刻第一绝缘层的一部分和蚀刻第 第一接触区域以形成暴露第一接触区域的初步开口。 该方法还包括蚀刻隔离图案以形成开口，在开口的侧壁上形成绝缘图案，并且形成与开口中的第一接触区域接触的布线结构。

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