公开(公告)号：US09691627B2

公开(公告)日：2017-06-27

申请号：US14963368

申请日：2015-12-09

Applicant: Samsung Electronics Co., Ltd

Inventor： Chan-Sic Yoon ,  Jiung Pak ,  Kiseok Lee ,  Chan Ho Park ,  Hyeonok Jung

IPC: H01L21/308 ,  H01L27/108

CPC classification number: H01L21/3088 ,  H01L21/3086 ,  H01L27/10814 ,  H01L27/10876

Abstract: A method of fabricating a semiconductor device includes forming a linear preliminary mask pattern in a first direction on a substrate. The preliminary mask pattern is patterned to provide a plurality of mask patterns that are aligned end-to-end with one another on the substrate and are separated by an exposed portion of the substrate between respective facing ends of the plurality of mask patterns. An auxiliary layer is formed to cover at least sidewalls of the facing ends to reduce a size of the exposed portion to provide a reduced exposed portion of the substrate and the reduced exposed portion of the substrate is etched to form a trench defining active patterns in the substrate aligned end-to-end with one another.

公开(公告)号：US10312105B2

公开(公告)日：2019-06-04

申请号：US15598861

申请日：2017-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-Sic Yoon ,  Jiung Pak ,  Kiseok Lee ,  Chan Ho Park ,  Hyeonok Jung

IPC: H01L21/308 ,  H01L27/108

Abstract: A method of fabricating a semiconductor device includes forming a linear preliminary mask pattern in a first direction on a substrate. The preliminary mask pattern is patterned to provide a plurality of mask patterns that are aligned end-to-end with one another on the substrate and are separated by an exposed portion of the substrate between respective facing ends of the plurality of mask patterns. An auxiliary layer is formed to cover at least sidewalls of the facing ends to reduce a size of the exposed portion to provide a reduced exposed portion of the substrate and the reduced exposed portion of the substrate is etched to form a trench defining active patterns in the substrate aligned end-to-end with one another.