公开(公告)号：US12211847B2

公开(公告)日：2025-01-28

申请号：US17382956

申请日：2021-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehoon Shin ,  Bongseok Suh ,  Daewon Kim ,  Sukhyung Park ,  Junggun You ,  Jaeyun Lee

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device may include a substrate including first and second active regions and a field region therebetween, first and second active patterns respectively provided on the first and second active regions, first and second source/drain patterns respectively provided on the first and second active patterns, a first channel pattern between the first source/drain patterns and a second channel pattern between the second source/drain patterns, and a gate electrode extended from the first channel pattern to the second channel pattern to cross the field region. Each of the first and second channel patterns may include semiconductor patterns, which are stacked to be spaced apart from each other. A width of a lower portion of the gate electrode on the field region may decrease with decreasing distance from a top surface of the substrate.

公开(公告)号：US11961914B2

公开(公告)日：2024-04-16

申请号：US18321962

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin Song ,  Junbeom Park ,  Bongseok Suh ,  Junggil Yang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795

Abstract: Integrated circuit devices including a fin shaped active region and methods of forming the same are provided. The devices may include a fin shaped active region, a plurality of semiconductor patterns on the fin shaped active region, a gate electrode on the plurality of semiconductor patterns, and source/drain regions on opposing sides of the gate electrode, respectively. The gate electrode may include a main gate portion extending on an uppermost semiconductor pattern and a sub-gate portion extending between two adjacent ones of the plurality of semiconductor patterns. The sub-gate portion may include a sub-gate center portion and sub-gate edge portions. In a horizontal cross-sectional view, a first width of the sub-gate center portion in a first direction may be less than a second width of one of the sub-gate edge portions in the first direction.

公开(公告)号：US11894463B2

公开(公告)日：2024-02-06

申请号：US18093877

申请日：2023-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin Song ,  Bongseok Suh ,  Junggil Yang ,  Soojin Jeong

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/7853 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392

Abstract: An integrated circuit includes a fin active region protruding from a substrate, a plurality of semiconductor patterns on an upper surface of the fin active region, a gate electrode that surrounds the plurality of semiconductor patterns and includes a main gate part on an uppermost one of the plurality of semiconductor patterns and sub gate parts between the plurality of semiconductor patterns, a spacer structure on a sidewall of the main gate part, and a source/drain region at a side of the gate electrode. The source/drain region is connected to the plurality of semiconductor patterns and contacts a bottom surface of the spacer structure. A top portion of the uppermost semiconductor pattern has a first width. A bottom portion of the uppermost semiconductor pattern has a second width smaller than the first width.

公开(公告)号：US11658075B2

公开(公告)日：2023-05-23

申请号：US17246778

申请日：2021-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmin Yoo ,  Juyoun Kim ,  Hyungjoo Na ,  Bongseok Suh ,  Jooho Jung ,  Euichul Hwang ,  Sungmoon Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/06 ,  H01L21/311 ,  H01L21/8238 ,  H01L27/118 ,  H01L21/762

CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L27/11807 ,  H01L2027/11816 ,  H01L2027/11829 ,  H01L2027/11861

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an active pattern, a gate electrode extending in a first direction and crossing the active pattern which extends in a second direction, a separation structure crossing the active pattern and extending in the first direction, a first gate dielectric pattern disposed on a side surface of the gate electrode, a second gate dielectric pattern disposed on a side surface of the separation structure, and a gate capping pattern covering a top surface of the gate electrode. A level of a top surface of the separation structure is higher than a level of a top surface of the gate capping pattern.

公开(公告)号：US11563121B2

公开(公告)日：2023-01-24

申请号：US17320617

申请日：2021-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin Song ,  Bongseok Suh ,  Junggil Yang ,  Soojin Jeong

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

Abstract: An integrated circuit includes a fin active region protruding from a substrate, a plurality of semiconductor patterns on an upper surface of the fin active region, a gate electrode that surrounds the plurality of semiconductor patterns and includes a main gate part on an uppermost one of the plurality of semiconductor patterns and sub gate parts between the plurality of semiconductor patterns, a spacer structure on a sidewall of the main gate part, and a source/drain region at a side of the gate electrode. The source/drain region is connected to the plurality of semiconductor patterns and contacts a bottom surface of the spacer structure. A top portion of the uppermost semiconductor pattern has a first width. A bottom portion of the uppermost semiconductor pattern has a second width smaller than the first width.

公开(公告)号：US11024741B2

公开(公告)日：2021-06-01

申请号：US16747870

申请日：2020-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin Song ,  Bongseok Suh ,  Junggil Yang ,  Soojin Jeong

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

Abstract: An integrated circuit includes a fin active region protruding from a substrate, a plurality of semiconductor patterns on an upper surface of the fin active region, a gate electrode that surrounds the plurality of semiconductor patterns and includes a main gate part on an uppermost one of the plurality of semiconductor patterns and sub gate parts between the plurality of semiconductor patterns, a spacer structure on a sidewall of the main gate part, and a source/drain region at a side of the gate electrode. The source/drain region is connected to the plurality of semiconductor patterns and contacts a bottom surface of the spacer structure. A top portion of the uppermost semiconductor pattern has a first width. A bottom portion of the uppermost semiconductor pattern has a second width smaller than the first width.