公开(公告)号：US20180083040A1

公开(公告)日：2018-03-22

申请号：US15813758

申请日：2017-11-15

Applicant: Samsung Display Co., Ltd.

Inventor： Young-Wook LEE ,  Woo-Geun LEE ,  Ki-Won KIM ,  Hyun-Jung LEE ,  Ji-Soo OH

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/768

CPC classification number: H01L27/124 ,  H01L21/76834 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/7869 ,  H01L29/78693

Abstract: A substrate including gate wirings including a gate line and a gate electrode disposed on a substrate, an oxide semiconductor layer pattern overlapping the gate electrode, a gate insulating layer disposed between the gate wirings and the oxide semiconductor layer pattern, data wirings including a data line crossing the gate line, a source electrode connected to one side of the oxide semiconductor layer pattern, and a drain electrode connected to another side of the oxide semiconductor layer, and an insulating pattern including a first portion which is disposed between the gate line and the data line and at least partially overlaps with both of the gate line and the data line.

公开(公告)号：US20190355752A1

公开(公告)日：2019-11-21

申请号：US16438385

申请日：2019-06-11

Applicant: Samsung Display Co., Ltd.

Inventor： Young-Wook LEE ,  Woo-Geun LEE ,  Ki-Won KIM ,  Hyun-Jung LEE ,  Ji-Soo OH

IPC: H01L27/12

Abstract: A substrate including a gate line and a gate electrode disposed on a substrate, an oxide semiconductor layer pattern overlapping the gate electrode, a gate insulating layer disposed between the gate electrode and the oxide semiconductor layer pattern, a data line intersecting the gate line, a source electrode electrically connected to the oxide semiconductor layer pattern, a drain electrode electrically connected to the oxide semiconductor layer, the drain electrode spaced apart from the source electrode, and an insulating pattern including a first portion, which is disposed between the gate line and the data line and at least partially overlaps with both of the gate line and the data line.

公开(公告)号：US20150311230A1

公开(公告)日：2015-10-29

申请号：US14793183

申请日：2015-07-07

Applicant: Samsung Display Co., Ltd.

Inventor： Young-Wook LEE ,  Woo-Geun LEE ,  Ki-Won KIM ,  Hyun-Jung LEE ,  Ji-Soo OH

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L21/76834 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/7869 ,  H01L29/78693

Abstract: A method of manufacturing a thin film transistor (TFT) array substrate includes forming a gate line and a gate electrode on a substrate, forming a gate-insulating layer and an oxide semiconductor layer on the gate line and the gate electrode, forming etch stop patterns at a thin-film transistor area and an area where the gate line and the data line overlap each other, forming a data conductor on the oxide semiconductor layer and the etch stop patterns, the data conductor comprising a source electrode and a drain electrode that constitute a TFT together with the gate electrode, and forming a data line extending in a direction intersecting the gate line.

Abstract translation: 制造薄膜晶体管（TFT）阵列基板的方法包括在基板上形成栅极线和栅电极，在栅极线和栅电极上形成栅极绝缘层和氧化物半导体层，形成蚀刻停止图案 在薄膜晶体管区域和栅极线和数据线彼此重叠的区域中，在氧化物半导体层和蚀刻停止图案上形成数据导体，数据导体包括源电极和漏极，构成 TFT与栅极电极一起形成，并且在与栅极线相交的方向上形成数据线。

公开(公告)号：US20150049276A1

公开(公告)日：2015-02-19

申请号：US14277526

申请日：2014-05-14

Applicant: Samsung Display Co., Ltd.

Inventor： Tae-Young CHOI ,  Bo Sung KIM ,  Jae Woo PARK ,  Hee Jun BYEON ,  Young-Wook LEE ,  Moon-Keun CHOI

IPC: H01L27/12 ,  G02F1/1362

CPC classification number: G02F1/136286 ,  G02F1/136204 ,  H01L27/0288 ,  H01L27/124

Abstract: A thin film transistor array panel includes: gate lines; data lines insulated from and crossing the gate lines; and shorting bars disposed outside of a display area in which the gate lines cross the data lines. The shorting bars overlap portions of the data lines disposed outside of the display area. The shorting bar includes a semiconductor material.

Abstract translation: 薄膜晶体管阵列面板包括：栅线; 数据线与栅极线绝缘和交叉; 以及设置在栅极线与数据线交叉的显示区域外的短路棒。 短路棒重叠布置在显示区域外部的数据线的部分。 短路棒包括半导体材料。

公开(公告)号：US20140147947A1

公开(公告)日：2014-05-29

申请号：US14168971

申请日：2014-01-30

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yu-Gwang JEONG ,  Young-Wook LEE ,  Sang-Gab KIM ,  Woo-Geun LEE ,  Min-Seok OH ,  Jang-Soo KIM ,  Kap-Soo YOON ,  Shin-Il CHOI ,  Hong-Kee CHIN ,  Seung-Ha CHOI ,  Seung-Hwan SHIM ,  Sung-Hoon YANG ,  Ki-Hun JEONG

IPC: H01L27/12

CPC classification number: H01L27/127 ,  H01L27/1214 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/66765

Abstract: Embodiments of the present invention relate to a thin film transistor and a manufacturing method of a display panel, and include forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an intrinsic semiconductor on the gate insulating layer, forming an extrinsic semiconductor on the intrinsic semiconductor, forming a data line including a source electrode and a drain electrode on the extrinsic semiconductor, and plasma-treating a portion of the extrinsic semiconductor between the source electrode and the drain electrode to form a protection member and ohmic contacts on respective sides of the protection member. Accordingly, the process for etching the extrinsic semiconductor and forming an inorganic insulating layer for protecting the intrinsic semiconductor may be omitted such that the manufacturing process of the display panel may be simplified, manufacturing cost may be reduced, and productivity may be improved.

Abstract translation: 本发明的实施例涉及薄膜晶体管和显示面板的制造方法，包括在基板上形成包括栅电极的栅极线，在栅电极上形成栅绝缘层，在栅电极上形成本征半导体 栅极绝缘层，在本征半导体上形成非本征半导体，在外部半导体上形成包括源电极和漏电极的数据线，以及对源电极和漏极之间的非本征半导体的一部分进行等离子体处理，以形成 保护构件和保护构件的相应侧上的欧姆接触。 因此，可以省略用于蚀刻外部半导体和形成用于保护本征半导体的无机绝缘层的工艺，从而可以简化显示面板的制造工艺，可以降低制造成本，并且可以提高生产率。