公开(公告)号：US20160197196A1

公开(公告)日：2016-07-07

申请号：US14800187

申请日：2015-07-15

Applicant: Samsung Display Co., Ltd.

Inventor： DONG GUN OH ,  Young Gu Kang ,  Sung In Ro ,  Jae Hak Lee ,  Sung Hoon Lim ,  Woong Ki Jeon

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L27/124 ,  H01L27/1214 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/1262 ,  H01L29/66742 ,  H01L29/78648 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/7869

Abstract: A thin film transistor is provided as follows. A first gate electrode and a second gate electrode are stacked on each other. A semiconductor layer is interposed between the first and second gate electrodes. A source electrode and a drain electrode are interposed between the semiconductor layer and the second gate electrode. A connection electrode connects electrically the first gate electrode and the second gate electrode. A first insulating film is interposed between the first gate electrode and the semiconductor layer. A second insulating film includes a first part interposed between the semiconductor layer and the second gate electrode and a second part interposed between the second gate electrode and the drain electrode. A third insulating film includes a first part interposed between the connection electrode and the second gate electrode.

Abstract translation: 如下提供薄膜晶体管。 第一栅电极和第二栅电极彼此堆叠。 半导体层介于第一和第二栅电极之间。 源电极和漏电极插入在半导体层和第二栅电极之间。 连接电极电连接第一栅电极和第二栅电极。 第一绝缘膜介于第一栅电极和半导体层之间。 第二绝缘膜包括插入在半导体层和第二栅电极之间的第一部分和介于第二栅电极和漏电极之间的第二部分。 第三绝缘膜包括插入在连接电极和第二栅电极之间的第一部分。

公开(公告)号：US11749195B2

公开(公告)日：2023-09-05

申请号：US17853129

申请日：2022-06-29

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yoon Jung Chai ,  Won Jun Lee ,  Chol Ho Kim ,  Sung Hoon Lim ,  Yoo Seok Jang

IPC: G09G3/3233 ,  G09G3/3266 ,  G09G3/20

CPC classification number: G09G3/3233 ,  G09G3/3266 ,  G09G3/2007 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2310/0294 ,  G09G2310/08 ,  G09G2320/0252

Abstract: A display device includes: active stages each include a scan output circuit outputting a scan clock signal to a first output terminal and a carry output circuit outputting a carry clock signal to a second output terminal, when a voltage of a first node is at a logic high level. The scan output circuit and carry output circuit output a scan signal of a turn-off level to the first output terminal when a voltage of a second node or a carry signal is at a logic high level. An interval between pulses of the carry clock signal generated during one frame period is the same, and at least two of intervals between pulses of the scan clock signal generated during the one frame period are different from each other.

公开(公告)号：US11127339B2

公开(公告)日：2021-09-21

申请号：US16875682

申请日：2020-05-15

Applicant: Samsung Display Co., Ltd.

Inventor： Kang Nam Kim ,  Sung Hoon Lim ,  Woo Geun Lee ,  Kyu Sik Cho ,  Jae Beom Choi

IPC: G09G3/3266 ,  G09G3/20

Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

公开(公告)号：US09754977B2

公开(公告)日：2017-09-05

申请号：US15370445

申请日：2016-12-06

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Dong Gun Oh ,  Young Gu Kang ,  Sung In Ro ,  Jae Hak Lee ,  Sung Hoon Lim ,  Woong Ki Jeon

IPC: H01L21/8234 ,  H01L27/12 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L27/124 ,  H01L27/1214 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/1262 ,  H01L29/66742 ,  H01L29/78648 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/7869

Abstract: A thin film transistor is provided as follows. A first gate electrode and a second gate electrode are stacked on each other. A semiconductor layer is interposed between the first and second gate electrodes. A source electrode and a drain electrode are interposed between the semiconductor layer and the second gate electrode. A connection electrode connects electrically the first gate electrode and the second gate electrode. A first insulating film is interposed between the first gate electrode and the semiconductor layer. A second insulating film includes a first part interposed between the semiconductor layer and the second gate electrode and a second part interposed between the second gate electrode and the drain electrode. A third insulating film includes a first part interposed between the connection electrode and the second gate electrode.