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公开(公告)号：US20150016580A1
公开(公告)日：2015-01-15
申请号：US14465739
申请日：2014-08-21
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Amir Amirkhany , Nasrin Jaffari
CPC classification number: H04L7/0012 , G09G5/008 , G09G2320/0693 , G09G2370/08 , H04L7/0338 , H04L43/087 , H04N5/04
Abstract: A system for forwarding a sample rate clock along with data. In one embodiment, a sample rate clock is sent by a transmitter, along with data, to one or more receivers. The receivers sample the received data using the received sampling clock. Delay adjust circuits in the transmitter adjust the delay of each transmitted data stream using delay error sensing and correction implemented in a back channel between the receivers and the transmitter.
Abstract translation: 用于将采样率时钟与数据一起转发的系统。 在一个实施例中，采样率时钟由发射机连同数据发送到一个或多个接收机。 接收机使用接收到的采样时钟对接收到的数据进行采样。 发射机中的延迟调整电路使用在接收机和发射机之间的后向通道中实现的延迟误差感测和校正来调整每个发射数据流的延迟。
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公开(公告)号：US20140314171A1
公开(公告)日：2014-10-23
申请号：US14061637
申请日：2013-10-23
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Mohammad Hekmat , Amir Amirkhany
CPC classification number: H03F3/45179 , H03F3/45183 , H03K5/082 , H04L25/4917
Abstract: A differential amplifier including: a first amplifier leg including a first transistor, and a second amplifier leg including a second transistor. Here, the first transistor is configured to have a bulk potential different from a bulk potential of the second transistor. The first amplifier leg and the second amplifier leg, together, may be configured to differentially amplify a received differential input signal. The differential amplifier may be configured to have an input offset voltage, which corresponds to the difference between the bulk potential of the first transistor and the bulk potential of the second transistor. The differential amplifier may be at an input stage of a comparator.
Abstract translation: 一种差分放大器，包括：包括第一晶体管的第一放大器支路和包括第二晶体管的第二放大器支路。 这里，第一晶体管被配置为具有与第二晶体管的体电势不同的体电位。 第一放大器支路和第二放大器支路在一起可以被配置为差分放大接收到的差分输入信号。 差分放大器可以被配置为具有对应于第一晶体管的体电势与第二晶体管的体电势之间的差的输入偏移电压。 差分放大器可以处于比较器的输入级。
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公开(公告)号：US10476707B2
公开(公告)日：2019-11-12
申请号：US16058896
申请日：2018-08-08
Applicant: Samsung Display Co., Ltd.
Inventor： Anup P. Jose , Amir Amirkhany , Mohammad Hekmat
Abstract: A two-stage decision feedback equalizer. The decision feedback equalizer is configured to receive serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer has an analog input and four digital outputs, and includes a first stage and a second stage. The first stage is connected to the analog input, and includes a half-rate predictive decision feedback equalizer consisting of current mode logic circuits. The second stage is connected to the first stage, and consists of complementary metal oxide semiconductor circuits.
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公开(公告)号：US20190272804A1
公开(公告)日：2019-09-05
申请号：US16057037
申请日：2018-08-07
Applicant: Samsung Display Co., Ltd.
Inventor： Amir Amirkhany , Mohammad Hekmat
Abstract: A circuit for duty cycle detection and correction, for a serial data transmitter. The circuit includes a pattern generator having a pattern data output configured to be selectively connected to the data input of the serial data transmitter, and a duty cycle detection circuit, connected to the output of the serial data transmitter. The pattern generator is configured to produce a pattern including a sequence including an odd number of consecutive zeros and a same number of consecutive ones. The duty cycle detection circuit is configured to measure a difference between a first interval and a second interval, in a signal at the output of the serial data transmitter, the first interval corresponding to the odd number of consecutive zeros within the sequence and the second interval corresponding to the odd number of consecutive ones within the sequence.
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公开(公告)号：US10401391B1
公开(公告)日：2019-09-03
申请号：US16054609
申请日：2018-08-03
Applicant: Samsung Display Co., Ltd.
Inventor： Da Wei , Mohammad Hekmat , Valentin Abramzon , Amir Amirkhany
Abstract: An on-chip scope and a method for operating the on-chip scope. The on-chip scope includes a provision for operating in one of two states, the effects of voltage offsets being different in the two states. A first voltage is measured in the first state, a second voltage is measured in the second state, and the two measurements are combined to generate a voltage estimate in which the effects of voltage offsets are reduced.
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Patent Agency Ranking
公开(公告)号：US10235952B2
公开(公告)日：2019-03-19
申请号：US15213112
申请日：2016-07-18
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Amir Amirkhany
Abstract: A display device comprises a display panel having a plurality of pixels arranged in pixel rows and pixel columns, and a source circuit. The source circuit includes a plurality of signal lines, each signal line coupled to each pixel of a pixel column; a plurality of column drivers, each column driver connected to one of the signal lines so as to transmit pixel voltages to the pixels of its respective pixel column, the pixel voltages corresponding to image data values for displaying an image upon the display panel; and a plurality of pixel refresh circuits. Each pixel refresh circuit corresponds to one of the signal lines and is coupled to the respective column driver so as to be arranged to determine a voltage stored in the corresponding pixel and to transmit a refresh signal to the respective column driver to refresh the voltage stored in the corresponding pixel.
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公开(公告)号：US09978663B2
公开(公告)日：2018-05-22
申请号：US14964460
申请日：2015-12-09
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： T. Gary Yip , Amir Amirkhany
IPC: H01L23/373 , H01L23/00 , H01L23/498 , H01L27/02
CPC classification number: H01L23/373 , H01L23/3735 , H01L23/49855 , H01L24/06 , H01L27/0248
Abstract: According to some embodiments of the present invention, a display device includes: a display panel; and an integrated circuit (IC) assembly coupled to the display panel, the IC assembly comprising: a flexible substrate; a first flexible thermally conductive layer on the flexible substrate; and an IC chip on the flexible substrate and thermally coupled to the first flexible thermally conductive layer.
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公开(公告)号：US09923664B2
公开(公告)日：2018-03-20
申请号：US14866798
申请日：2015-09-25
Applicant: Samsung Display Co., Ltd.
Inventor： Amir Amirkhany
IPC: H04L1/00
CPC classification number: H04L1/0009 , H04L1/0041 , H04L1/0042 , H04L25/03057 , H04L25/03885
Abstract: A method for transmitting an input stream of data across a serial link including a serial channel. The method includes segmenting the stream of data into blocks of bits to form input blocks, and for each input block, calculating a measure of burst error probability, forming an output block and a modification signaling bit from the input block, transmitting the output block, and transmitting the modification signaling bit. The forming of the output block and the modification signaling bit from the input block includes, when the measure of burst error probability exceeds a set threshold: modifying the input block to form the output block, and asserting the modification signaling bit.
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公开(公告)号：US09680436B1
公开(公告)日：2017-06-13
申请号：US15083211
申请日：2016-03-28
Applicant: Samsung Display Co., Ltd.
Inventor： Gaurav Malhotra , Amir Amirkhany
CPC classification number: H03G3/3036 , H03H2021/0065 , H04B1/16 , H04L25/03057 , H04L25/03114 , H04L25/03885 , H04L2025/03636
Abstract: A system and method for setting analog front end in a serial receiver. The serial receiver includes a decision feedback equalizer. During initialization, taps of the decision feedback equalizer other than the zeroth tap are disabled, and the zeroth tap is used to estimate the amplitude of the signal at the output of the analog front end. The analog front end gain is iteratively adjusted until the estimated value of the zeroth tap is within a set range.
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公开(公告)号：US09674008B2
公开(公告)日：2017-06-06
申请号：US14340463
申请日：2014-07-24
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Mohammad Hekmat , Amir Amirkhany
CPC classification number: H04L25/03057 , G09G5/006 , G09G2310/0297 , G09G2330/021 , H03M1/002 , H03M1/70 , H04L25/03146 , H04L25/03878
Abstract: A predictive decision feedback equalizer using body bias of one or more field effect transistors (FETs) to provide an offset for a predictive tap. In one embodiment, a predictive tap of the predictive decision feedback equalizer includes a differential amplifier composed of two FETs in a differential amplifier configuration, and the body bias of one or both FETs is controlled to provide an offset in the differential amplifier. In one embodiment a current DAC driving a DAC resistor is used to provide the body bias voltage, and a feedback circuit, including a replica circuit forming the maximum possible DAC output voltage, is used to control the bias of the current sources of the current DAC.
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