公开(公告)号：US20170324405A1

公开(公告)日：2017-11-09

申请号：US15361594

申请日：2016-11-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Albert Martinez ,  Michel Agoyan

IPC: H03K17/00 ,  H03K19/003 ,  H03K5/159

CPC classification number: H03K17/005 ,  G06F7/58 ,  H03K3/84 ,  H03K5/159 ,  H03K19/003 ,  H03K19/1737

Abstract: A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.

公开(公告)号：US10187040B2

公开(公告)日：2019-01-22

申请号：US15700475

申请日：2017-09-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Albert Martinez

IPC: H03H11/26 ,  H03L7/06

Abstract: A delaying element includes a first XOR logic gate and a second XOR logic gate. A first input of the first XOR logic gate defines an input terminal. A first input of the second XOR logic gate is connected to an output of the first XOR logic gate. An output of the second XOR logic gate defines an output terminal. The second inputs of the first and second XOR logic gates are connected to a second input terminal.

公开(公告)号：US10103721B2

公开(公告)日：2018-10-16

申请号：US15361594

申请日：2016-11-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Albert Martinez ,  Michel Agoyan

IPC: H03K17/00 ,  H03K5/159 ,  H03K19/003 ,  G06F7/58 ,  H03K3/84 ,  H03K19/173

Abstract: A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.

公开(公告)号：US20180269855A1

公开(公告)日：2018-09-20

申请号：US15700475

申请日：2017-09-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Albert Martinez

IPC: H03H11/26

CPC classification number: H03H11/265 ,  G06F7/58 ,  H03K19/21 ,  H04L9/06

Abstract: A delaying element includes a first XOR logic gate and a second XOR logic gate. A first input of the first XOR logic gate defines an input terminal. A first input of the second XOR logic gate is connected to an output of the first XOR logic gate. An output of the second XOR logic gate defines an output terminal. The second inputs of the first and second XOR logic gates are connected to a second input terminal.

公开(公告)号：US08902600B2

公开(公告)日：2014-12-02

申请号：US13765064

申请日：2013-02-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Albert Martinez ,  Pascal Fornara

IPC: H05K5/00 ,  H05K1/02 ,  H01G5/16 ,  H01H1/00 ,  H01H59/00 ,  H05K3/30 ,  H01G5/04

CPC classification number: H05K1/02 ,  H01G5/04 ,  H01G5/16 ,  H01H1/0036 ,  H01H59/0009 ,  H05K3/30 ,  Y10T29/49155

Abstract: A thermally deformable assembly is formed in an integrated-circuit metallization level. The physical behavior of the metal forming the assembly brings the assembly into contact with a stop-forming body when subjected to a temperature change caused by a current flow. A natural rollback to the initial configuration in which the assembly is a certain distance away from the body is prevented. The state or configuration of the assembly is determined by a capacitive reader.

Abstract translation: 热变形组件形成在集成电路金属化层中。 形成组件的金属的物理行为使得组件在受到由电流引起的温度变化时与停止成形体接触。 防止组装距离身体一定距离的初始构造的自然回滚。 组件的状态或配置由电容式读取器确定。