公开(公告)号：US10162551B2

公开(公告)日：2018-12-25

申请号：US15195352

申请日：2016-06-28

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Marco Leo ,  Paolo Rosingana ,  Marco Castellano ,  Alessandro Giuliano Locardi

IPC: G06F3/06 ,  G01D9/00 ,  H03M7/30

Abstract: A signal interface has a compression unit and a data memory. The compression unit is configured to input an input datum from signal data generated by at least one sensor and further configured to identify the presence or absence of at least one repetition condition in the input datum. If the presence of the at least one repetition condition of the input datum is identified, the compression unit encodes the input datum in a compressed way to generate a compressed datum and saves the compressed datum in the data memory. If the presence of the at least one repetition condition of the input datum is not identified, the compression unit saves the uncompressed input datum in the data memory.

公开(公告)号：US20170314923A1

公开(公告)日：2017-11-02

申请号：US15373282

申请日：2016-12-08

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Marco Leo ,  Marco Castellano

IPC: G01C19/5776

CPC classification number: G01C19/5776 ,  G01C25/005

Abstract: A MEMS inertial sensor device has a package and a gyroscopic sensor, an accelerometric sensor, and an ASIC electronic circuit integrated within the package. The ASIC is operatively coupled to the gyroscopic sensor and the accelerometric sensor for supplying at an output a gyroscopic signal indicative of an angular velocity and an acceleration signal indicative of an acceleration acting on the MEMS inertial sensor device. The ASIC is provided with a processing module, which may be of a purely hardware type, for processing jointly the gyroscopic signal and the accelerometric signal and determining a bias value present on the gyroscopic signal.

公开(公告)号：US11587378B2

公开(公告)日：2023-02-21

申请号：US17012495

申请日：2020-09-04

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Marco Castellano ,  Marco Leo

IPC: G07C5/08 ,  G06N20/00 ,  B60W50/06 ,  H03M7/30

Abstract: A device includes sensing circuitry, compression circuitry, and a memory. The sensing circuitry, in operation, generates sensor data. The compression circuitry is coupled to the sensing circuitry, and, in operation, determines environmental contexts based on variation rates of sensor data and compresses sensor data based on determined environmental contexts. The compressed data is stored in the memory.

公开(公告)号：US10921122B2

公开(公告)日：2021-02-16

申请号：US15889891

申请日：2018-02-06

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Marco Leo ,  Paolo Rosingana ,  Marco Castellano

IPC: G01C9/06 ,  G01P15/18 ,  G06F13/24

Abstract: A sensor includes an accelerometer, which, in operation, generates accelerometer data, and digital signal processing circuitry. The digital signal processing circuitry, in operation, generates, based on the generated accelerometer data, a value indicative of a cosine of an angle between an acceleration vector associated with current accelerometer data and a reference acceleration vector, compares the generated value indicative of the cosine of the angle between the vector associated with current accelerometer data and the reference acceleration vector with one or more thresholds and generates a tilt signal based on the comparison of the generated value indicative of the cosine of the angle between the vector associated with current accelerometer data and the reference acceleration vector with the one or more thresholds. The tilt signal may be used as an interrupt signal to an application processor.

公开(公告)号：US10445285B2

公开(公告)日：2019-10-15

申请号：US15639543

申请日：2017-06-30

Applicant: STMicroelectronics S.R.L.

Inventor： Marco Leo ,  Alessandra Maria Rizzo Piazza Roncoroni ,  Marco Castellano

IPC: G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F13/12 ,  G06F13/364

Abstract: An integrated data concentrator, so-called “sensor hub”, for a multi-sensor MEMS system, implements: a first interface module, for interfacing, in a normal operating mode, with a microprocessor through a first communication bus; and a second interface module, for interfacing, in the normal operating mode, with a plurality of sensors through a second communication bus; the sensor hub further implements a pass-through operating mode, distinct from the normal operating mode, in which it sets the microprocessor in direct communication with the sensors, through the first communication bus and the second communication bus. In particular, the sensor hub implements the direct pass-through operating mode in a totally digital manner.

公开(公告)号：US09710413B2

公开(公告)日：2017-07-18

申请号：US14313769

申请日：2014-06-24

Applicant: STMicroelectronics S.r.l.

Inventor： Marco Leo ,  Alessandra Maria Rizzo Piazza Roncoroni ,  Marco Castellano

IPC: G06F13/24 ,  G06F13/00 ,  G06F13/14 ,  G06F13/40 ,  G06F13/38

CPC classification number: G06F13/4286 ,  G06F13/124 ,  G06F13/364 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027 ,  G06F2213/0016 ,  Y02D10/14 ,  Y02D10/151

Abstract: An integrated data concentrator, so-called “sensor hub”, for a multi-sensor MEMS system, implements: a first interface module, for interfacing, in a normal operating mode, with a microprocessor through a first communication bus; and a second interface module, for interfacing, in the normal operating mode, with a plurality of sensors through a second communication bus; the sensor hub further implements a pass-through operating mode, distinct from the normal operating mode, in which it sets the microprocessor in direct communication with the sensors, through the first communication bus and the second communication bus. In particular, the sensor hub implements the direct pass-through operating mode in a totally digital manner.

公开(公告)号：US09672155B2

公开(公告)日：2017-06-06

申请号：US14664630

申请日：2015-03-20

Applicant: STMicroelectronics S.r.l.

Inventor： Marco Leo ,  Paolo Rosingana ,  Marco Castellano

IPC: G06F12/00 ,  G06F12/0875 ,  G01D9/00

CPC classification number: G06F12/0875 ,  G01D9/005 ,  G06F2212/1056 ,  G06F2212/451

Abstract: A plurality of sensors provide respective output data rates, with a first sensor that has a highest output data rate, while one or more other sensors have output data rates that are submultiples of the aforesaid highest output data rate. The data signals coming from the sensors are stored in a memory, e.g., a FIFO memory, by storing the data signals of the first sensor at the aforesaid highest output data rate, accompanying storage of the data signals coming from said first sensor with storage of the data signals coming from the sensors as supplied by said other sensors at the aforesaid submultiple output data rates, so that the data signals are stored in the memory according to a repeated pattern that is common to the various sensors.

公开(公告)号：US12299596B2

公开(公告)日：2025-05-13

申请号：US17360977

申请日：2021-06-28

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Luca Gandolfi ,  Marco Castellano ,  Marco Leo

IPC: G06N5/04 ,  G01C19/5712 ,  G01P1/00 ,  G01P15/08 ,  G06N20/00

Abstract: System, method, and circuitry for utilizing sequential input inertial sensor data to calculate recursive features for training a machine learning algorithm or for classifying the data as a known class. The recursive feature values of a current data sample are calculating based on comparisons between the current data sample value and previous recursive feature values. The recursive features include a recursive maximum, recursive minimum, recursive peak to peak, recursive average, recursive root mean square, and recursive variance.

公开(公告)号：US10459862B2

公开(公告)日：2019-10-29

申请号：US16219803

申请日：2018-12-13

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Eugenio Miluzzi ,  Marco Leo ,  Marco Castellano

IPC: G06F13/12 ,  G06F13/364 ,  G06F13/42 ,  G06F13/40

Abstract: A system includes a multi-conductor bus, a master device coupled to the multi-conductor bus, and at least one slave device coupled to the multi-conductor bus. The multi-conductor bus has a clock line and a data line. The master device is arranged to transmit an address configuration sequence, and the at least one slave device is arranged to configurably determine its own address based on at least one portion of the address configuration sequence. The at least one slave device has a physical address configuration input coupled to either a fixed voltage potential or a changing voltage potential. The at least one slave device is arranged with a first address during a pre-initialization state and arranged with a second address during a post-initialization state. During the post-initialization state, the first address and the second address are a same address when the address configuration sequence represents the first address and the first address and the second address are different addresses when the address configuration sequence does not represent the first address.

公开(公告)号：US20180150424A1

公开(公告)日：2018-05-31

申请号：US15363932

申请日：2016-11-29

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Eugenio Miluzzi ,  Marco Leo ,  Marco Castellano

IPC: G06F13/364 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/364 ,  G06F13/404 ,  G06F13/4282

Abstract: A system includes a multi-conductor bus, a master device coupled to the multi-conductor bus, and at least one slave device coupled to the multi-conductor bus. The multi-conductor bus has a clock line and a data line. The master device is arranged to transmit an address configuration sequence, and the at least one slave device is arranged to configurably determine its own address based on at least one portion of the address configuration sequence. The at least one slave device has a physical address configuration input coupled to either a fixed voltage potential or a changing voltage potential. The at least one slave device is arranged with a first address during a pre-initialization state and arranged with a second address during a post-initialization state. During the post-initialization state, the first address and the second address are a same address when the address configuration sequence represents the first address and the first address and the second address are different addresses when the address configuration sequence does not represent the first address.