公开(公告)号：US20200058667A1

公开(公告)日：2020-02-20

申请号：US16401205

申请日：2019-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon BAEK

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  H01L27/02

Abstract: A three-dimensional semiconductor device comprises a stack structure on a lower structure, a vertical channel structure passing through the stack structure, and a first vertical support structure passing through the stack structure and spaced apart from the vertical channel structure. The stack structure includes interlayer insulation layers and gate horizontal patterns, alternately stacked in a vertical direction perpendicular to an upper surface of the lower structure. The vertical channel structure and the first vertical support structure have different cross-sectional shapes. The vertical channel structure further includes a channel semiconductor layer. The vertical channel structure includes first and second vertical regions, and a width variation portion between the first and second vertical regions. The interlayer insulation layers include an intermediate interlayer insulation layer adjacent to the width variation portion. The intermediate interlayer insulation layer has the same thickness as that of an interlayer insulation layer adjacent in the vertical direction.

公开(公告)号：US20220130851A1

公开(公告)日：2022-04-28

申请号：US17569497

申请日：2022-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Hyoung KIM ,  Kwang Soo KIM ,  Seok Cheon BAEK ,  Geun Won LIM

IPC: H01L27/11575 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11548

Abstract: A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first, block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.

公开(公告)号：US20210375904A1

公开(公告)日：2021-12-02

申请号：US17403544

申请日：2021-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon BAEK

IPC: H01L27/11556 ,  H01L27/02 ,  G11C5/06 ,  H01L27/11582

Abstract: A three-dimensional semiconductor device comprises a stack structure on a lower structure, a vertical channel structure passing through the stack structure, and a first vertical support structure passing through the stack structure and spaced apart from the vertical channel structure. The stack structure includes interlayer insulation layers and gate horizontal patterns, alternately stacked in a vertical direction perpendicular to an upper surface of the lower structure. The vertical channel structure and the first vertical support structure have different cross-sectional shapes. The vertical channel structure further includes a channel semiconductor layer. The vertical channel structure includes first and second vertical regions, and a width variation portion between the first and second vertical regions. The interlayer insulation layers include an intermediate interlayer insulation layer adjacent to the width variation portion. The intermediate interlayer insulation layer has the same thickness as that of an interlayer insulation layer adjacent in the vertical direction.

公开(公告)号：US20210288072A1

公开(公告)日：2021-09-16

申请号：US17333407

申请日：2021-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon BAEK

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L29/66 ,  H01L27/11568 ,  H01L27/11575

Abstract: A semiconductor device includes a substrate having a cell region and a connection region adjacent to the cell region. A lower stack structure and an upper stack structure are disposed on the substrate. A channel structure is provided to pass through the upper stack structure and the lower stack structure. A distance between a lower extension line portion included in an uppermost one of a plurality of lower interconnection layers and an upper extension line portion included in a lowermost one of a plurality of upper interconnection layers is less than a distance between a lower gate electrode portion included in the uppermost one of the plurality of lower interconnection layers and an upper gate electrode portion included in the lowermost one of the plurality of upper interconnection layers.

公开(公告)号：US20200091185A1

公开(公告)日：2020-03-19

申请号：US16365827

申请日：2019-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon BAEK

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11568 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having a cell region and a connection region adjacent to the cell region. A lower stack structure and an upper stack structure are disposed on the substrate. A channel structure is provided to pass through the upper stack structure and the lower stack structure. A distance between a lower extension line portion included in an uppermost one of a plurality of lower interconnection layers and an upper extension line portion included in a lowermost one of a plurality of upper interconnection layers is less than a distance between a lower gate electrode portion included in the uppermost one of the plurality of lower interconnection layers and an upper gate electrode portion included in the lowermost one of the plurality of upper interconnection layers.

公开(公告)号：US20190214404A1

公开(公告)日：2019-07-11

申请号：US16257357

申请日：2019-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Seon AHN ,  Ji Sung CHEON ,  Young Jin KWON ,  Seok Cheon BAEK ,  Woong Seop LEE

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/4234

Abstract: A three-dimensional semiconductor device includes an upper substrate, a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape, and at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region.