公开(公告)号：US11916002B2

公开(公告)日：2024-02-27

申请号：US17551938

申请日：2021-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Kyung Don Mun

IPC: H01L23/498 ,  H01L23/31 ,  H01L25/18 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/49822 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/08 ,  H01L25/18 ,  H01L2224/08235

Abstract: Disclosed is a semiconductor package comprising a package substrate, an interposer substrate on the package substrate and including a first redistribution substrate, a second redistribution substrate on a bottom surface of the first redistribution substrate, and an interposer molding layer between the first redistribution substrate and the second redistribution substrate, a connection substrate on the interposer substrate and having a connection hole that penetrates the connection substrate, a first semiconductor chip on the interposer substrate and in the connection hole, a second semiconductor chip on the interposer substrate, in the connection hole and horizontally spaced apart from the first semiconductor chip, and a connection semiconductor chip in the interposer molding layer and on the bottom surface of the first redistribution substrate.

公开(公告)号：US11837537B2

公开(公告)日：2023-12-05

申请号：US17403233

申请日：2021-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongju Cho ,  Myungsam Kang ,  Younggwan Ko ,  Gun Lee ,  Jaekul Lee

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L23/3157 ,  H01L23/49531 ,  H01L23/49534 ,  H01L23/5283 ,  H01L24/09 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2924/3511

Abstract: A fan-out semiconductor package includes a first connection structure having first and second surfaces, a first semiconductor chip disposed on the first surface, a first encapsulant disposed on the first surface and covering at least a portion of the first semiconductor chip, a second semiconductor chip disposed on the second surface, one or more first metal members disposed on the second surface, one or more second metal members disposed on the second surface, a second encapsulant disposed on the second surface and respectively covering at least portions of the second semiconductor chip and the first and second metal members, and a second connection structure disposed on an opposite side of a side of the second encapsulant, on which the first connection structure is disposed.

公开(公告)号：US20230075027A1

公开(公告)日：2023-03-09

申请号：US18055805

申请日：2022-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungsam Kang ,  Yongjin Park ,  Youngchan Ko

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L23/552 ,  H01L25/16

Abstract: A semiconductor package includes an interconnect structure having a first surface and a second surface opposing the first surface, and including a redistribution pattern and a vertical connection conductor, a first semiconductor chip disposed for a first inactive surface to oppose the first surface, a second semiconductor chip disposed on the first surface of the interconnect structure and disposed for the second inactive surface to oppose the first surface; a first encapsulant encapsulating the first and second semiconductor chips, a backside wiring layer disposed on the first encapsulant, a wiring structure connecting the redistribution pattern to the backside wiring layer, a heat dissipation member disposed on the second surface and connected to the vertical connection conductor.

公开(公告)号：US11562966B2

公开(公告)日：2023-01-24

申请号：US17195823

申请日：2021-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Bongju Cho

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/10

Abstract: A semiconductor package includes a first redistribution structure having a first surface in which a first pad and a second pad are embedded and including a first redistribution layer thereon, and a vertical connection structure including a land layer and a pillar layer. The land layer is embedded in the first surface of the first redistribution structure, and a width of an upper surface of the land layer is narrower than a width of a lower surface of the pillar layer.

公开(公告)号：US11508639B2

公开(公告)日：2022-11-22

申请号：US16917251

申请日：2020-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungsam Kang ,  Yongjin Park ,  Youngchan Ko

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/367 ,  H01L23/538 ,  H01L23/552 ,  H01L21/683 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package includes an interconnect structure having a first surface and a second surface opposing the first surface, and including a redistribution pattern and a vertical connection conductor, a first semiconductor chip disposed for a first inactive surface to oppose the first surface, a second semiconductor chip disposed on the first surface of the interconnect structure and disposed for the second inactive surface to oppose the first surface; a first encapsulant encapsulating the first and second semiconductor chips, a backside wiring layer disposed on the first encapsulant, a wiring structure connecting the redistribution pattern to the backside wiring layer, a heat dissipation member disposed on the second surface and connected to the vertical connection conductor.

公开(公告)号：US11329014B2

公开(公告)日：2022-05-10

申请号：US16703279

申请日：2019-12-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Changbae Lee ,  Bongju Cho ,  Younggwan Ko ,  Yongkoon Lee ,  Moonil Kim ,  Youngchan Ko

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/522

Abstract: A semiconductor package includes: a connection structure including one or more redistribution layers; a core structure disposed on a surface of the connection structure; a semiconductor chip disposed on the surface and including connection pads electrically connected to the redistribution layers of the connection structure; a first encapsulant disposed on the surface and covering at least a portion of each of the core structure and the semiconductor chip; an antenna substrate disposed on the first encapsulant and including one or more wiring layers, at least a portion of the wiring layers including an antenna pattern; and a through via penetrating at least a portion of each of the connection structure, the core structure, the first encapsulant, and the antenna substrate.

公开(公告)号：US20210210427A1

公开(公告)日：2021-07-08

申请号：US16988831

申请日：2020-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Kyungdon Mun

IPC: H01L23/522 ,  H01L23/36 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip having a connection pad connected to the first redistribution layer; a vertical connection conductor electrically connected to the connection pad by the first redistribution layer; a core member having a first through-hole accommodating the semiconductor chip and a second through-hole accommodating the vertical connection conductor; an encapsulant filling the first and second through-holes; and a redistribution member including a second redistribution layer. The vertical connection conductor and the core member include a same material. A width of a lower surface of the vertical connection conductor is wider than that of an upper surface thereof, a width of a lower end of the first through-hole is narrower than that of an upper end thereof, and a width of a lower end of the second through-hole is narrower than that of an upper end thereof.

公开(公告)号：US12159826B2

公开(公告)日：2024-12-03

申请号：US17476670

申请日：2021-09-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Kyungdon Mun

IPC: H01L23/522 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package includes a support substrate having connection wirings disposed therein. At least one capacitor is disposed on the support substrate. The capacitor has first and second electrodes that are exposed from an upper surface of the support substrate. A redistribution wiring layer covers the upper surface of the support substrate. The redistribution wiring layer has redistribution wirings electrically connected to the connection wirings and the first and second electrodes respectively. A semiconductor chip is disposed on the redistribution wiring layer. The semiconductor chip has chip pads that are electrically connected to the redistribution wirings and outer connectors disposed on a lower surface of the support substrate and electrically connected to the connection wirings.

公开(公告)号：US12094817B2

公开(公告)日：2024-09-17

申请号：US18125529

申请日：2023-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Kyungdon Mun

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36

CPC classification number: H01L23/5226 ,  H01L23/31 ,  H01L23/36 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20

Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip having a connection pad connected to the first redistribution layer; a vertical connection conductor electrically connected to the connection pad by the first redistribution layer; a core member having a first through-hole accommodating the semiconductor chip and a second through-hole accommodating the vertical connection conductor; an encapsulant filling the first and second through-holes; and a redistribution member including a second redistribution layer. The vertical connection conductor and the core member include a same material. A width of a lower surface of the vertical connection conductor is wider than that of an upper surface thereof, a width of a lower end of the first through-hole is narrower than that of an upper end thereof, and a width of a lower end of the second through-hole is narrower than that of an upper end thereof.

公开(公告)号：US12040297B2

公开(公告)日：2024-07-16

申请号：US18166869

申请日：2023-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Kyungdon Mun

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L24/14 ,  H01L23/49811 ,  H01L23/5226 ,  H01L24/05

Abstract: A semiconductor package includes a redistribution structure including an insulating layer and a redistribution layer on the insulating layer, and having a first surface and a second surface opposing the first surface, and an under-bump metal (UBM) structure including an UBM pad protruding from the first surface of the redistribution structure, and an UBM via penetrating through the insulating layer and connecting the redistribution layer and the UBM pad. A lower surface of the UBM via has a first area in contact with the UBM pad, and a second area having a step configuration relative to the first area and that extends outwardly of the first area.