Fan-out semiconductor package
    11.
    发明授权

    公开(公告)号:US10748856B2

    公开(公告)日:2020-08-18

    申请号:US16103199

    申请日:2018-08-14

    Abstract: A fan-out semiconductor package includes: a core member having a first through-hole and including a dummy metal layer; a first semiconductor chip disposed in the first through-hole and having a first active surface having first connection pads disposed thereon and a first inactive surface opposing the first active surface; a first encapsulant covering at least portions of the core member and the first semiconductor chip and filling at least portions of the first through-hole; and a first connection member disposed on the core member and the first active surface of the first semiconductor chip and including a first redistribution layer electrically connected to the first connection pads, wherein the dummy metal layer is electrically insulated from signal patterns of the first redistribution layer.

    Fan-out semiconductor package
    12.
    发明授权

    公开(公告)号:US10475748B2

    公开(公告)日:2019-11-12

    申请号:US15981651

    申请日:2018-05-16

    Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is connected to the stopper layer; a first encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; an electronic component disposed on the other surface of the frame opposing one surface of the frame in which the semiconductor chip is disposed; a second encapsulant covering at least portions of the electronic component; and a connection member disposed on the frame and an active surface of the semiconductor chip and including a redistribution layer, wherein the connection pads and the electronic component are electrically connected to each other through the wiring layers and the redistribution layer.

    Fan-out semiconductor package
    13.
    发明授权

    公开(公告)号:US10410961B2

    公开(公告)日:2019-09-10

    申请号:US15978727

    申请日:2018-05-14

    Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion, and having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface and disposed on the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the plurality of wiring layers of the frame and the connection pads of the semiconductor chip to each other. The active surface of the semiconductor chip and an upper surface of the encapsulant have a step portion therebetween.

    Semiconductor package
    15.
    发明授权

    公开(公告)号:US11075152B2

    公开(公告)日:2021-07-27

    申请号:US16715697

    申请日:2019-12-16

    Abstract: A semiconductor package includes a first connection member including a first redistribution layer, a first frame disposed on the first connection member, a first semiconductor chip disposed on a first through-portion and having a connection pad, a first encapsulant covering a portion of each of the first frame and the first semiconductor chip and filling at least a portion of the first through-portion, a second connection member disposed on the first encapsulant and including a second redistribution layer, a second semiconductor chip disposed on the second connection member and having a second connection pad, a second encapsulant covering a portion of the second semiconductor chip, and a first through-via penetrating through the first frame, the first encapsulant, and a portion of the first connection member, and electrically connecting the first and second redistribution layers to each other.

    Semiconductor package and antenna module comprising the same

    公开(公告)号:US11062999B2

    公开(公告)日:2021-07-13

    申请号:US16570055

    申请日:2019-09-13

    Abstract: A semiconductor package includes a core structure having a first through-hole and including a frame having an opening, a passive component disposed in the opening, a first encapsulant covering the frame and the passive component, a first metal layer disposed on an inner surface of the first through-hole, and a second metal layer disposed on an inner surface of the opening; a first semiconductor chip disposed in the first through-hole and having a first connection pad; a second encapsulant covering the core structure and the first semiconductor chip; a connection structure disposed on the core structure and the first semiconductor chip and including a redistribution layer; and a metal pattern layer disposed on the second encapsulant. The first and second metal layers are connected to the metal pattern layer through first and second metal vias having heights different from each other.

    Semiconductor package
    17.
    发明授权

    公开(公告)号:US10818604B2

    公开(公告)日:2020-10-27

    申请号:US16414016

    申请日:2019-05-16

    Abstract: A semiconductor package includes a semiconductor chip having connection pads on one surface thereof, a first encapsulant covering at least portions of the semiconductor chip, and a connection structure disposed on the one surface of the semiconductor chip and including one or more redistribution layers electrically connected to the connection pads. A wiring structure is disposed on one surface of the first encapsulant opposing another surface of the first encapsulant facing towards the connection structure. The wiring structure has a passive component embedded therein, and includes one or more wiring layers electrically connected to the passive component. The one or more redistribution layers and the one or more wiring layers are electrically connected to each other.

Patent Agency Ranking