公开(公告)号：US12148708B2

公开(公告)日：2024-11-19

申请号：US18141568

申请日：2023-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Koon Lee ,  Myung Sam Kang ,  Young Gwan Ko ,  Young Chan Ko ,  Chang Bae Lee

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/552 ,  H01L23/66 ,  H01L25/16 ,  H01Q1/38

Abstract: A semiconductor package including a core structure, in which a first and second semiconductor chips and passive components are embedded, a connection structure disposed on a first side of the core structure, and including a redistribution layer electrically connected to the first and second semiconductor chips and the passive components, and a metal pattern layer and a backside wiring layer disposed on a second side of the core structure opposing the first side, and spaced apart from each other. The core structure includes a first metal layer surrounding the first semiconductor chip, a second metal layer surrounding the first semiconductor chip, and the first metal layer, a third metal layer surrounding the second semiconductor chip, and a fourth metal layer surrounding the second semiconductor chip, the passive components, and the third metal layer, and each of the first to fourth metal layers is electrically connected to the metal pattern layer.

公开(公告)号：US11894310B2

公开(公告)日：2024-02-06

申请号：US17194438

申请日：2021-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung Sam Kang ,  Ki Ju Lee ,  Young Chan Ko ,  Jeong Seok Kim ,  Bong Ju Cho

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/552 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/367

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2924/3025

Abstract: A fan-out semiconductor package including a first redistribution layer; a first semiconductor chip on the first redistribution layer; an interconnector on the first redistribution layer and spaced apart from the first semiconductor chip; a molded layer covering the interconnector and side surfaces of the first semiconductor chip; and a second redistribution layer on the molded layer, wherein the interconnector includes a metal ball and is electrically connected to the first redistribution layer, the second redistribution layer includes a first line wiring, and a first via electrically connected to the first line wiring, the first via is connected to the interconnector, and a part of the first via is in the molded layer.

公开(公告)号：US11062999B2

公开(公告)日：2021-07-13

申请号：US16570055

申请日：2019-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Koon Lee ,  Myung Sam Kang ,  Young Gwan Ko ,  Young Chan Ko ,  Chang Bae Lee

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/16 ,  H01L23/66 ,  H01L23/552 ,  H01Q1/38 ,  H01L23/13 ,  H01L21/48

Abstract: A semiconductor package includes a core structure having a first through-hole and including a frame having an opening, a passive component disposed in the opening, a first encapsulant covering the frame and the passive component, a first metal layer disposed on an inner surface of the first through-hole, and a second metal layer disposed on an inner surface of the opening; a first semiconductor chip disposed in the first through-hole and having a first connection pad; a second encapsulant covering the core structure and the first semiconductor chip; a connection structure disposed on the core structure and the first semiconductor chip and including a redistribution layer; and a metal pattern layer disposed on the second encapsulant. The first and second metal layers are connected to the metal pattern layer through first and second metal vias having heights different from each other.

公开(公告)号：US11676907B2

公开(公告)日：2023-06-13

申请号：US17353074

申请日：2021-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Koon Lee ,  Myung Sam Kang ,  Young Gwan Ko ,  Young Chan Ko ,  Chang Bae Lee

IPC: H01L21/48 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/16 ,  H01L23/66 ,  H01L23/552 ,  H01Q1/38 ,  H01L23/13

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5386 ,  H01L23/552 ,  H01L23/66 ,  H01L24/05 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L25/16 ,  H01Q1/38 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/82101 ,  H01L2924/1421 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3025

Abstract: A method including forming a frame having an opening, forming a first metal layer, forming a first encapsulant, forming an insulation layer on the first metal layer, forming a first through-hole and a second through-hole penetrating the insulation layer and the first encapsulant, forming a second metal layer and a third metal layer, forming a second encapsulant, forming a first metal via and a second metal via penetrating the second encapsulant and a metal pattern layer on the second encapsulant, and forming a connection structure. The first metal layer and the second metal layer respectively are formed to extend to a surface of each of the first encapsulant and the frame, facing the metal pattern layer, and the first metal layer and the second metal layer are connected to the metal pattern layer through the first metal via and the second metal via having heights different from each other.