公开(公告)号：US20240172426A1

公开(公告)日：2024-05-23

申请号：US18346942

申请日：2023-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyeok AHN ,  Myeongdong LEE

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/34

Abstract: A semiconductor device may include a device isolation layer on a substrate and defining an active region; and a word line structure in a gate trench defined by the device isolation layer and the active region. The word line structure may include a word line on a gate dielectric layer. The word line may include a second material layer including a doped semiconductor material on a first material layer, may have a first region having a first width and a second region having a second width, which may be wider than the first width. The second material layer may include a first material portion in the first region and a second material portion in the second region. The doped semiconductor material may be a first concentration in the first material portion and a second concentration in the second material portion, which may be lower than the first concentration.

公开(公告)号：US20240098987A1

公开(公告)日：2024-03-21

申请号：US18243122

申请日：2023-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyeok AHN

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/09 ,  H10B12/315

Abstract: A semiconductor device includes a substrate having a cell array area and a peripheral circuit area, a plurality of first active areas defined in the cell array area and at least one second active area defined in the peripheral circuit area, a plurality of bit lines disposed in the substrate, a plurality of cell pad structures including a first conductive layer, a first intermediate layer, and a first metal layer having a first height from an upper surface of the first intermediate layer, and a peripheral circuit gate electrode disposed on the peripheral circuit area of the substrate and including a second conductive layer, a second intermediate layer, and a second metal layer having a second height from an upper surface of the second intermediate layer sequentially disposed on the at least one second active area, the second height being less than the first height.

公开(公告)号：US20230354588A1

公开(公告)日：2023-11-02

申请号：US18117604

申请日：2023-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Junhyeok AHN ,  Keunnam KIM ,  Chan-Sic YOON ,  Myeong-Dong LEE

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/02

Abstract: A semiconductor memory device includes a semiconductor substrate; a device isolation layer defining an active portion in the semiconductor substrate; a bit line structure intersecting the active portion on the semiconductor substrate; a first conductive pad between the bit line structure and the active portion; a bit line contact pattern between the first conductive pad and the bit line structure; a first bit line contact spacer covering a first sidewall of the first conductive pad; and a second bit line contact spacer covering a second sidewall of the first conductive pad, wherein the first conductive pad has a flat bottom surface that is in contact with a top surface of the active portion, and a width of the first bit line contact spacer is different from a width of the second bit line contact spacer.

公开(公告)号：US20230298999A1

公开(公告)日：2023-09-21

申请号：US18047704

申请日：2022-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyeok AHN ,  Myeong-Dong LEE

IPC: H01L23/528 ,  H01L21/762 ,  H10B12/00 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76224 ,  H01L27/10885 ,  H01L27/10888 ,  H01L23/53271 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10823

Abstract: A semiconductor memory device may include a device isolation pattern in a substrate and defining a first active section of the substrate and a second active section of the substrate, a first bit line crossing the center of the first active section, a second bit line crossing a center of the second active section, a bit-line contact between the first bit line and a center of the first active section, and a storage node pad on an end of the second active section. The first and second active sections may be spaced apart from each other. The center of the first active section may be adjacent to the end of the second active section. A level of a bottom surface of the first bit line may be lower than a level of a bottom surface of the second bit line.

公开(公告)号：US20240397707A1

公开(公告)日：2024-11-28

申请号：US18381785

申请日：2023-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangkyu SUN ,  Goro CHOI ,  Hyo-Sub KIM ,  Junhyeok AHN ,  Eunkyung CHA ,  Dongmin CHOI ,  Sanghyun CHOI

IPC: H10B12/00 ,  H01L29/423

Abstract: A semiconductor memory device includes a substrate having a cell array area and a core area near the cell array area, the cell array area including a direct contact hole exposing an active region, a buried contact in the cell array area, the buried contact being connected to a storage element, a direct contact in the cell array area, the direct contact including an upper layer and a lower layer, the upper layer including a metal, and the lower layer being in the direct contact hole in direct contact with the active region and including a silicide of the metal, bit lines in contact with the upper layer of the direct contact, and word lines crossing the bit lines.

公开(公告)号：US20240306378A1

公开(公告)日：2024-09-12

申请号：US18241335

申请日：2023-09-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyeok AHN

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/02 ,  H10B12/315 ,  H10B12/50

Abstract: A semiconductor device includes a substrate having a cell active region; a word line on the cell active region; a bit line electrically connected to the cell active region; a connection structure in the word line; and a word line contact plug in contact with the connection structure. The word line may include a gate electrode, and the connection structure may be disposed on the gate electrode. The connection structure and the gate electrode may include different materials from each other.

公开(公告)号：US20230422486A1

公开(公告)日：2023-12-28

申请号：US18109442

申请日：2023-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Jongmin KIM ,  Hyo-Sub KIM ,  Hui-Jung KIM ,  Sohyun PARK ,  Junhyeok AHN ,  Chan-Sic YOON ,  Myeong-Dong LEE ,  Woojin JEONG ,  Wooyoung CHOI

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/34 ,  H10B12/053 ,  H10B12/485

Abstract: A semiconductor device includes a cell active pattern including a first portion and a second portion that are spaced apart from each other; a gate structure between the first portion and the second portion of the cell active pattern; a bit-line contact on the first portion of the cell active pattern; a connection pattern on the second portion of the cell active pattern; and a cell separation pattern in contact with the bit-line contact and the connection pattern, wherein the cell separation pattern includes a first sidewall in contact with the connection pattern and a second sidewall in contact with the bit-line contact, an upper portion of the second sidewall of the cell separation pattern is in contact with the bit-line contact, and a lower portion of the second sidewall of the cell separation pattern is spaced apart from the bit-line contact.

公开(公告)号：US20230137846A1

公开(公告)日：2023-05-04

申请号：US17969966

申请日：2022-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyeok AHN ,  Sohyun PARK ,  Hyosub KIM

IPC: H01L27/108

Abstract: Provided is a semiconductor device including a substrate including a cell array area and a peripheral circuit area and including a plurality of first active areas defined in the cell array area and at least one second active area defined in the peripheral circuit area; a plurality of bit lines arranged in the cell array area of the substrate and extending in a first direction; a plurality of cell pad structures arranged between the bit lines and each including a first conductive layer, a first intermediate layer, and a first metal layer that are sequentially arranged on a top surface of the first active area; and a peripheral circuit gate electrode disposed on the peripheral circuit area of the substrate and including a second conductive layer, a second intermediate layer, and a second metal layer sequentially arranged on the at least one second active area.

公开(公告)号：US20230112907A1

公开(公告)日：2023-04-13

申请号：US17861479

申请日：2022-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Sub KIM ,  Junhyeok AHN ,  Myeong-Dong LEE ,  Hui-Jung KIM ,  Kiseok LEE ,  Jihun LEE ,  Yoosang HWANG

IPC: H01L27/108

Abstract: A semiconductor memory device and a method of fabricating a semiconductor memory device, the device including a first impurity region in a substrate; a first bit line that crosses over the substrate and is connected to the first impurity region; a bit-line contact between the first bit line and the first impurity region; and a contact ohmic layer between the bit-line contact and the first impurity region, wherein a width of a bottom surface of the bit-line contact is greater than a width of a bottom surface of the contact ohmic layer.

公开(公告)号：US20220336464A1

公开(公告)日：2022-10-20

申请号：US17530818

申请日：2021-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyeok AHN ,  Kiseok LEE ,  Huijung KIM

IPC: H01L27/108

Abstract: A semiconductor device includes: a substrate including a cell area and an interface area; a gate electrode disposed in the substrate within the cell area and extending in a first direction; a plurality of bit lines intersecting the gate electrode and extending in a second direction intersecting the first direction, wherein the plurality of bit lines includes a plurality of first bit lines and a plurality of second bit lines alternately disposed in the first direction; edge spacers disposed within the interface area and contacting the plurality of second bit lines; and edge insulating layers disposed between the edge spacers and contacting the plurality of first bit lines, wherein at least a portion of each of the edge insulating layers is disposed within the interface area.