公开(公告)号：US10121744B2

公开(公告)日：2018-11-06

申请号：US15491227

申请日：2017-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunjung Choi ,  Kivin Im ,  Dongbok Lee ,  Inseak Hwang

IPC: H01L23/528 ,  H01L27/108 ,  H01L27/115

Abstract: Semiconductor devices are provided including a plurality of nonlinear bit lines formed on a substrate including a plurality of active areas; a plurality of word lines that pass through the plurality of active areas; an integral spacer that covers two sidewalls of the plurality of nonlinear bit lines and defines a plurality of spaces that expose two adjacent ones of the plurality of active areas; two conductive patterns that respectively abut on the two adjacent active areas in one of the plurality of spaces that is selected; and a contact separating insulation layer that is formed between the two conductive patterns in the one selected space.

公开(公告)号：US09768115B2

公开(公告)日：2017-09-19

申请号：US14701777

申请日：2015-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunjung Choi ,  Kivin Im ,  Dongbok Lee ,  Inseak Hwang

IPC: H01L27/108 ,  H01L27/115 ,  H01L23/528

CPC classification number: H01L23/528 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided including a plurality of nonlinear bit lines formed on a substrate including a plurality of active areas; a plurality of word lines that pass through the plurality of active areas; an integral spacer that covers two sidewalls of the plurality of nonlinear bit lines and defines a plurality of spaces that expose two adjacent ones of the plurality of active areas; two conductive patterns that respectively abut on the two adjacent active areas in one of the plurality of spaces that is selected; and a contact separating insulation layer that is formed between the two conductive patterns in the one selected space.

公开(公告)号：US20160307773A1

公开(公告)日：2016-10-20

申请号：US14990353

申请日：2016-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mongsup Lee ,  Yoonho Son ,  Sang-Jun Lee ,  Munkwon Kang ,  Kyunghyun Kim ,  Inseak Hwang

IPC: H01L21/311

CPC classification number: H01L21/31116 ,  H01L21/02063 ,  H01L21/7682 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888

Abstract: A substrate having an insulating layer including an oxide is loaded into a chamber, and at least a part of the insulating layer is removed by injecting a process gas including an etching source gas into the chamber. The removal process is performed in a pulse type in which a first period and a second period are repeated a plurality of times. The etching source gas is supplied at a first flow rate during the first period and is supplied at a second flow rate less than the first flow rate during the second period. A temperature of the inside of the chamber remains at 100° C. or more during the removal process.

Abstract translation: 具有包含氧化物的绝缘层的衬底被加载到腔室中，并且通过将包括蚀刻源气体的处理气体注入到室中来去除绝缘层的至少一部分。 去除处理以多次重复第一周期和第二周期的脉冲类型执行。 蚀刻源气体在第一时段期间以第一流量供应，并且在第二时段期间以小于第一流量的第二流量供应。 在除去过程中，室内温度保持在100℃或更高。

公开(公告)号：US20140332905A1

公开(公告)日：2014-11-13

申请号：US14444200

申请日：2014-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwangwook Lee ,  Inseak Hwang

IPC: H01L29/36 ,  H01L29/78

CPC classification number: H01L29/36 ,  H01L29/772 ,  H01L29/78

Abstract: A method of fabricating a semiconductor device includes forming a gate dielectric layer comprising an oxide, and at least one conductive layer on a substrate, forming a mask on the conductive layer and patterning the at least one conductive layer by etching the at least one conductive layer using the mask as an etch mask to thereby form a gate electrode, wherein the oxide of the gate dielectric layer and the material of the at least one conductive layer are selected such that a byproduct of the etching of the at least one conductive layer, formed on the mask during the etching of the at least one conductive layer, comprises an oxide having a higher etch rate with respect to an etchant than the oxide of the gate dielectric layer.

Abstract translation: 一种制造半导体器件的方法包括：形成包含氧化物的栅极电介质层和在衬底上的至少一个导电层，在导电层上形成掩模，并通过蚀刻所述至少一个导电层来图案化所述至少一个导电层 使用掩模作为蚀刻掩模从而形成栅电极，其中选择栅介质层的氧化物和至少一个导电层的材料，使得形成的至少一个导电层的蚀刻副产物形成 在蚀刻所述至少一个导电层期间在掩模上包含相对于蚀刻剂具有比栅极电介质层的氧化物更高的蚀刻速率的氧化物。