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    Semiconductor device
    12.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10224096B2

    公开(公告)日：2019-03-05

    申请号：US15921226

    申请日：2018-03-14

    Applicant: Renesas Electronics Corporation

    Inventor： Yuichiro Ishii ,  Atsushi Miyanishi ,  Kazumasa Yanagisawa

    IPC: G11C5/14 ,  G11C11/417 ,  H03K19/00 ,  H03K17/687 ,  H01L23/528 ,  H01L27/11 ,  H01L29/10

    Abstract: A semiconductor device includes: a first power source line for supplying a first voltage; a second power source line for supplying a second voltage; a memory circuit coupled with the first and second power source lines; a first switch which electrically coupling the first power source line with the second power source line and electrically decoupling the first power source line from the second power source line, in response to a control signal; a second switch which electrically coupling the first power source line with the second power source line and electrically decoupling the first power source line from the second power source line, in response to the control signal, wherein a memory circuit includes a memory cell array and a peripheral circuit, wherein a memory cell array includes a plurality of memory cells, the memory cells coupled with the second power source line.

    SEMICONDUCTOR DEVICE
    13.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180204612A1

    公开(公告)日：2018-07-19

    申请号：US15921226

    申请日：2018-03-14

    Applicant: Renesas Electronics Corporation

    Inventor： Yuichiro Ishii ,  Atsushi Miyanishi ,  Kazumasa Yanagisawa

    IPC: G11C11/417 ,  H01L29/10 ,  H01L23/528 ,  H01L27/11

    CPC classification number: G11C11/417 ,  H01L23/5286 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1095 ,  H03K17/6871 ,  H03K19/0016

    Abstract: A semiconductor device includes: a first power source line for supplying a first voltage; a second power source line for supplying a second voltage; a memory circuit coupled with the first and second power source lines; a first switch which electrically coupling the first power source line with the second power source line and electrically decoupling the first power source line from the second power source line, in response to a control signal; a second switch which electrically coupling the first power source line with the second power source line and electrically decoupling the first power source line from the second power source line, in response to the control signal, wherein a memory circuit includes a memory cell array and a peripheral circuit, wherein a memory cell array includes a plurality of memory cells, the memory cells coupled with the second power source line.

    SEMICONDUCTOR STORAGE DEVICE
    14.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE 有权

    公开(公告)号：US20170278566A1

    公开(公告)日：2017-09-28

    申请号：US15619821

    申请日：2017-06-12

    Applicant: Renesas Electronics Corporation

    Inventor： Yuichiro Ishii

    IPC: G11C11/419 ,  G11C5/14 ,  G11C7/12

    CPC classification number: G11C11/419 ,  G11C5/148 ,  G11C7/12 ,  G11C2207/2227

    Abstract: A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.

    Semiconductor device
    15.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09559693B2

    公开(公告)日：2017-01-31

    申请号：US14866544

    申请日：2015-09-25

    Applicant: Renesas Electronics Corporation

    Inventor： Yuichiro Ishii ,  Atsushi Miyanishi ,  Kazumasa Yanagisawa

    IPC: H03K19/00 ,  H03K17/687

    CPC classification number: G11C11/417 ,  H01L23/5286 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1095 ,  H03K17/6871 ,  H03K19/0016

    Abstract: A semiconductor device includes a first power source line which accepts the supply of power in the active mode, a second power source line which accepts the supply of power in the active mode and the standby mode, a memory circuit to be coupled with the first and second power source lines and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array, a peripheral circuit and a second switch. Each of the first and second switches includes a first PMOS transistor and a second PMOS transistor.

    Abstract translation: 一种半导体器件包括接受主动模式下的电力供给的第一电源线，接受主动模式和备用模式的电力供给的第二电源线，与第一和第二电力线耦合的存储电路， 第二电源线和第一开关，其将第一电源线与第二电源线以活动模式电耦合，并且在待机模式下将第一电源线与第二电源线电耦合。 存储器电路包括存储器阵列，外围电路和第二开关。 第一和第二开关中的每一个包括第一PMOS晶体管和第二PMOS晶体管。

    SEMICONDUCTOR DEVICE
    16.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20160126953A1

    公开(公告)日：2016-05-05

    申请号：US14866544

    申请日：2015-09-25

    Applicant: Renesas Electronics Corporation

    Inventor： Yuichiro Ishii ,  Atsushi MIYANISHI ,  Kazumasa YANAGISAWA

    IPC: H03K19/00 ,  H03K17/687

    CPC classification number: G11C11/417 ,  H01L23/5286 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1095 ,  H03K17/6871 ,  H03K19/0016

    Abstract: A semiconductor device includes a first power source line which accepts the supply of power in the active mode, a second power source line which accepts the supply of power in the active mode and the standby mode, a memory circuit to be coupled with the first and second power source lines and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array, a peripheral circuit and a second switch. Each of the first and second switches includes a first PMOS transistor and a second PMOS transistor.

    Abstract translation: 一种半导体器件包括接受主动模式下的电力供给的第一电源线，接受主动模式和备用模式的电力供给的第二电源线，与第一和第二电力线耦合的存储电路， 第二电源线和第一开关，其将第一电源线与第二电源线以活动模式电耦合，并且在待机模式下将第一电源线与第二电源线电耦合。 存储器电路包括存储器阵列，外围电路和第二开关。 第一和第二开关中的每一个包括第一PMOS晶体管和第二PMOS晶体管。

    Semiconductor storage device with smaller driving force precharge
    17.
    发明授权
    Semiconductor storage device with smaller driving force precharge 有权
    具有较小驱动力预充电的半导体存储装置

    公开(公告)号：US09196353B2

    公开(公告)日：2015-11-24

    申请号：US14634743

    申请日：2015-02-28

    Applicant: Renesas Electronics Corporation

    Inventor： Yuichiro Ishii

    IPC: G11C7/12 ,  G11C11/419 ,  G11C5/14

    CPC classification number: G11C11/419 ,  G11C5/148 ,  G11C7/12 ,  G11C2207/2227

    Abstract: A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.

    Abstract translation: 半导体存储装置包括由驱动晶体管，转移晶体管和负载晶体管组成的SRAM存储单元，连接到与存储单元连接的位线的I / O电路，以及操作模式控制电路， 在恢复待机模式和正常操作模式之间的I / O电路的模式，其中I / O电路包括将数据写入位线的写入驱动器，从位线读取数据的读出放大器，插入的第一开关 在位线和写入驱动器之间，插入在位线和读出放大器之间的第二开关，预充电位线的预充电电路，以及根据信号控制第一和第二开关和预充电电路的控制电路 从操作模式控制电路。

    Semiconductor memory device
    20.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US10360091B2

    公开(公告)日：2019-07-23

    申请号：US16152052

    申请日：2018-10-04

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yuichiro Ishii ,  Atsushi Miyanishi ,  Yoshikazu Saito

    IPC: G06F7/02 ,  H03M13/00 ,  G06F11/07

    Abstract: The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.

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