Abstract:
A Field Effect Transistor (FET) having a substrate; a plurality of active regions disposed on the substrate; and a laterally extending finger-like control electrode disposed on a portion of a surface of the substrate. The active regions are laterally spaced one from the other successively along the laterally extending finger-like control electrode. The laterally extending finger-like control electrode controls a flow of carriers through each one of the plurality of active regions between a source electrode and a drain electrode.
Abstract:
A Field Effect Transistor (FET) having: a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads; a gate contact connected to the gate electrodes of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed on a surface in a two-dimensional array.
Abstract:
A Field Effect Transistor (FET) having a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads. The FET includes; a gate contact connected to the gate electrode of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed in a loop configuration.
Abstract:
A Field Effect Transistor (FET) having: a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads; a gate contact connected to the gate electrodes of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed on a surface in a two-dimensional array.