公开(公告)号：US20140070212A1

公开(公告)日：2014-03-13

申请号：US14022721

申请日：2013-09-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hidehiro FUJIWARA ,  Makoto YABUUCHI ,  Koji NII ,  Yoshikazu SAITO

IPC: G06K19/07

CPC classification number: G11C29/44 ,  G06K19/0722 ,  G11C7/10 ,  G11C11/417 ,  G11C29/06 ,  G11C29/12 ,  G11C2029/4402

Abstract: A semiconductor device having a capability of generating chip identification information includes: an SRAM macro having a plurality of memory cells arranged in rows and columns; a test address storage unit configured to store a test address; a self-diagnostic circuit configured to output the test address based on a result of confirmation of operation of the memory cell selected by the test address; and an identification information generation circuit configured to generate chip identification information based on the test address which is output by the self-diagnostic circuit.

Abstract translation: 具有产生芯片识别信息的能力的半导体器件包括：具有以行和列排列的多个存储单元的SRAM宏; 被配置为存储测试地址的测试地址存储单元; 自诊断电路，被配置为基于由测试地址选择的存储器单元的操作的确认结果来输出测试地址; 以及识别信息生成电路，被配置为基于由所述自诊断电路输出的测试地址来生成芯片识别信息。