公开(公告)号：US20170162683A1

公开(公告)日：2017-06-08

申请号：US15437559

申请日：2017-02-21

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO ,  Yoshinao MIURA ,  Takashi INOUE

IPC: H01L29/778 ,  H01L29/15 ,  H01L29/423 ,  H01L29/40 ,  H01L23/535 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/027 ,  H01L29/205 ,  H01L29/06

CPC classification number: H01L29/7787 ,  H01L21/0274 ,  H01L21/3065 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer, a third nitride semiconductor layer formed over the second nitride semiconductor layer, a fourth nitride semiconductor layer formed over the third nitride semiconductor layer, a trench that penetrates the fourth nitride semiconductor layer and reaches as far as the third nitride semiconductor layer, a gate electrode disposed by way of a gate insulation film in the trench, a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode, and a coupling portion for coupling the first electrode and the first nitride semiconductor layer.

公开(公告)号：US20170047437A1

公开(公告)日：2017-02-16

申请号：US15216817

申请日：2016-07-22

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Ichiro MASUMOTO ,  Shinichi MIYAKE ,  Hiroshi KAWAGUCHI

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/06 ,  H01L29/66 ,  H01L29/808 ,  H01L21/02 ,  H01L21/324 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7783 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/2258 ,  H01L29/1066 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/808

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has an impurity-containing potential fixed layer, and a gate electrode. A drain electrode and a source electrode are formed on the opposite sides of the gate electrode. An interlayer insulation film is formed between the gate electrode and the drain electrode, and between the gate electrode and the source electrode. The concentration of the inactivating element in the portion of the potential fixed layer under the drain electrode is higher than the concentration of the inactivating element in the portion of the potential fixed layer under the source electrode. The film thickness of the portion of the interlayer insulation film between the gate electrode and the drain electrode is different from the film thickness of the portion of the interlayer insulation film between the gate electrode and the source electrode.

Abstract translation: 改善了半导体器件的特性。 半导体器件具有含杂质的电位固定层和栅电极。 漏电极和源电极形成在栅电极的相对侧上。 在栅电极和漏电极之间以及栅电极和源电极之间形成层间绝缘膜。 在漏电极下方的电位固定层部分中的灭活元件的浓度高于源电极下的电位固定层部分中的钝化元件的浓度。 栅电极和漏电极之间的层间绝缘膜的部分的膜厚度与栅电极和源电极之间的层间绝缘膜的部分的膜厚不同。

公开(公告)号：US20160240648A1

公开(公告)日：2016-08-18

申请号：US15142601

申请日：2016-04-29

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro OKAMOTO ,  Tatsuo NAKAYAMA ,  Takashi INOUE

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/7787 ,  H01L21/28264 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7789

Abstract: A semiconductor device includes a first nitride semiconductor layer formed above a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer, a trench passing through the second nitride semiconductor layer and into the first nitride semiconductor layer, a gate insulation film formed in the trench, and a gate electrode disposed by way of the gate insulation film in an inside of the trench. The corner of the trench between a side wall of the trench and a bottom of the trench includes a rounded shape, and a corner of the gate insulation film in contact with the corner of the trench includes a rounded shape.

Abstract translation: 半导体器件包括形成在衬底上的第一氮化物半导体层，形成在第一氮化物半导体层上并且具有比第一氮化物半导体层的带隙大的带隙的第二氮化物半导体层，穿过第二氮化物半导体层 并且形成在沟槽中的第一氮化物半导体层，栅极绝缘膜以及沟槽内部通过栅极绝缘膜设置的栅电极。 沟槽的侧壁和沟槽的底部之间的沟槽的角部包括圆形形状，并且与沟槽的角部接触的栅极绝缘膜的角部包括圆形。

公开(公告)号：US20170288046A1

公开(公告)日：2017-10-05

申请号：US15463320

申请日：2017-03-20

Applicant: Renesas Electronics Corporation

Inventor： Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO ,  Hiroshi KAWAGUCHI ,  Tatsuo NAKAYAMA

IPC: H01L29/778 ,  H01L29/417 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/10

CPC classification number: H01L29/7787 ,  H01L21/0254 ,  H01L21/30612 ,  H01L29/0657 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/66462 ,  H01L29/7786

Abstract: A property of a semiconductor device (high electron mobility transistor) is improved. A semiconductor device having a buffer layer, a channel layer, an electron supply layer, a mesa type cap layer, a source electrode, a drain electrode and a gate insulating film covering the cap layer, and a gate electrode formed on the gate insulating film, is configured as follows. The cap layer and the gate electrode are separated from each other by the gate insulating film, and side surfaces of the cap layer, the side surfaces being closer to the drain electrode and the source electrode, have tapered shapes. For example, a taper angle (θ1) of the side surface of the cap layer (mesa portion) is equal to or larger than 120 degrees. By this configuration, a TDDB life can be effectively improved, and variation in an ON-resistance can be effectively suppressed.

公开(公告)号：US20170054016A1

公开(公告)日：2017-02-23

申请号：US15340956

申请日：2016-11-01

Applicant: Renesas Electronics Corporation

Inventor： Shinichi MIYAKE ,  Tatsuo NAKAYAMA

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7787 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7785 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a buffer layer, a channel layer, a barrier layer, and agate electrode over a substrate, the gate electrode being disposed in a first opening with agate insulating film in between, the first opening running up to the middle of the channel layer through the barrier layer. The concentration of two-dimensional electron gas in a first region on either side of a second opening that will have a channel is controlled to be lower than the concentration of two-dimensional electron gas in a second region between an end of the first region and a source or drain electrode. The concentration of the two-dimensional electron gas in the first region is thus decreased, thereby the conduction band-raising effect of polarization charge is prevented from being reduced. This prevents a decrease in threshold potential, and thus improves normally-off operability.

Abstract translation: 半导体器件包括衬底上的缓冲层，沟道层，阻挡层和玛瑙电极，栅电极设置在第一开口中，其间具有玛瑙绝缘膜，第一开口延伸到通道的中间 穿过阻挡层。 在具有通道的第二开口的任一侧的第一区域中的二维电子气的浓度被控制为低于在第一区域的端部与第二区域的端部之间的第二区域中的二维电子气体的浓度 源极或漏极。 因此，第一区域中的二维电子气的浓度降低，从而防止极化电荷的导带效应降低。 这防止了阈值电位的降低，从而提高了常态可操作性。

公开(公告)号：US20160005846A1

公开(公告)日：2016-01-07

申请号：US14829216

申请日：2015-08-18

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro OKAMOTO ,  Tatsuo NAKAYAMA ,  Takashi INOUE ,  Hironobu MIYAMOTO

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/423 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer formed over the first semiconductor layer, a gate insulating film contacting the second semiconductor layer, and a gate electrode facing the second semiconductor layer via the gate insulating film. The first semiconductor layer includes an Alxα1-xN layer (α includes Ga or In, and 0

Abstract translation: 半导体器件包括第一半导体层，形成在第一半导体层上的第二半导体层，与第二半导体层接触的栅极绝缘膜，以及经由栅极绝缘膜与第二半导体层相对的栅电极。 第一半导体层包括Al xα1-x N层（α包括Ga或In，并且0

公开(公告)号：US20150076511A1

公开(公告)日：2015-03-19

申请号：US14550118

申请日：2014-11-21

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro OKAMOTO ,  Yuji ANDO ,  Tatsuo NAKAYAMA ,  Takashi INOUE ,  Kazuki OTA

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/205 ,  H01L29/20 ,  H01L29/201

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In1−zAlzN (0≦z≦1), a channel layer having a composition of: AlxGa1−xN (0≦x≦1) or InyGa1−yN (0≦y≦1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.

Abstract translation: 场效应晶体管包括衬底和设置在衬底上的半导体层，其中半导体层包括设置在衬底上的下阻挡层，生长Ga面，晶格弛豫并具有组成In 1-z Al z N（0＆nl; z＆nl E; 1），具有以下组成的沟道层：Al x Ga 1-x N（0＆amp; nlE; x＆nlE; 1）或In y Ga 1-y N（0＆nlE; y＆nlE; 1）。 或提供在栅极绝缘膜上并与栅极绝缘膜配置的栅电极，栅极配置在栅极绝缘膜上，栅电极配置在栅极绝缘膜上， 位于源电极和漏电极之间的区域。

公开(公告)号：US20140264274A1

公开(公告)日：2014-09-18

申请号：US14198430

申请日：2014-03-05

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO ,  Ryohei NEGA ,  Masaaki KANAZAWA ,  Takashi INOUE

IPC: H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/7787

Abstract: To improve performance of a semiconductor device. For example, on the assumption that a superlattice layer is inserted between a buffer layer and a channel layer, a concentration of acceptors introduced into nitride semiconductor layers forming a part of the superlattice layer is higher than a concentration of acceptors introduced into nitride semiconductor layers forming the other part of the superlattice layer. That is, the concentration of acceptors introduced into the nitride semiconductor layers having a small band gap is higher than the concentration of acceptors introduced into the nitride semiconductor layers having a large band gap.

Abstract translation: 提高半导体器件的性能。 例如，假设超晶格层被插入在缓冲层和沟道层之间，则导入形成超晶格层的一部分的氮化物半导体层中的受主的浓度高于形成氮化物半导体层的受主的浓度 超晶格层的另一部分。 也就是说，导入具有小带隙的氮化物半导体层的受主的浓度高于导入具有大带隙的氮化物半导体层的受主的浓度。

公开(公告)号：US20140209980A1

公开(公告)日：2014-07-31

申请号：US14229645

申请日：2014-03-28

Applicant: Renesas Electronics Corporation

Inventor： Takashi INOUE ,  Tatsuo NAKAYAMA ,  Yasuhiro OKAMOTO ,  Hironobu MIYAMOTO

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/778 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/432 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

Abstract: A method for manufacturing a semiconductor device includes forming a buffer layer made of a nitride semiconductor, forming a channel layer made of a nitride semiconductor over the buffer layer, forming a barrier layer made of a nitride semiconductor over the channel layer, forming a cap layer made of a nitride semiconductor over the barrier layer, forming a gate insulating film so as to in contact with the cap layer; and forming a gate electrode over the gate insulating film, wherein compression strains are generated at an interface between the cap layer and the barrier layer and an interface between the channel layer and the buffer layer and a tensile strain is generated at an interface between the barrier layer and the channel layer by controlling compositions of the cap layer, the barrier layer, the channel layer, and the buffer layer.

Abstract translation: 一种半导体器件的制造方法，包括：形成由氮化物半导体构成的缓冲层，在所述缓冲层上形成由氮化物半导体构成的沟道层，在所述沟道层上形成由氮化物半导体构成的阻挡层，形成覆盖层 由阻挡层上的氮化物半导体形成，形成栅极绝缘膜以与盖层接触; 以及在所述栅极绝缘膜上形成栅电极，其中在所述覆盖层和所述阻挡层之间的界面处产生压缩应变，以及在所述沟道层和所述缓冲层之间的界面处产生压应变，并且在所述栅极之间的界面处产生拉伸应变 层和沟道层，通过控制盖层，阻挡层，沟道层和缓冲层的组成。

公开(公告)号：US20190019886A1

公开(公告)日：2019-01-17

申请号：US16135298

申请日：2018-09-19

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO

IPC: H01L29/778 ,  H01L21/265 ,  H01L21/266 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06 ,  H01L21/02 ,  H01L29/20 ,  H01L29/10 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/7787 ,  H01L21/02694 ,  H01L21/2258 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/266 ,  H01L29/0688 ,  H01L29/1066 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66462 ,  H01L29/7783

Abstract: A semiconductor device includes a codoped layer, a channel layer, a barrier layer, and a gate electrode disposed in a trench extending through the barrier layer and reaching a middle point in the channel layer via a gate insulating film. On both sides of the gate electrode, a source electrode and a drain electrode are formed. On the source electrode side, an n-type semiconductor region is disposed to fix a potential and achieve a charge removing effect while, on the drain electrode side, a p-type semiconductor region is disposed to improve a drain breakdown voltage. By introducing hydrogen into a region of the codoped layer containing Mg as a p-type impurity in an amount larger than that of Si as an n-type impurity where the n-type semiconductor region is to be formed, it is possible to inactivate Mg and provide the n-type semiconductor region.