公开(公告)号：US11887935B2

公开(公告)日：2024-01-30

申请号：US17345399

申请日：2021-06-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takehiro Ueda

IPC: H01L23/544 ,  H01L21/304 ,  H01L21/66 ,  H01L23/31 ,  H01L23/482 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L23/544 ,  H01L21/304 ,  H01L22/12 ,  H01L22/32 ,  H01L23/3171 ,  H01L23/4824 ,  H01L29/402 ,  H01L29/7813 ,  H01L22/00 ,  H01L2223/5444 ,  H01L2223/5448 ,  H01L2223/54433 ,  H01L2223/54453

Abstract: A method for manufacturing a semiconductor device includes forming semiconductor devices from a semiconductor wafer and identifying a position of the semiconductor device in the semiconductor wafer, wherein the forming the semiconductor devices includes forming a first repeating pattern including i semiconductor devices each having a unique pattern, forming a second repeating pattern including j semiconductor devices each having a unique pattern, defining semiconductor devices on the semiconductor wafer such that each of the k semiconductor devices has a unique pattern based on the first and second repeating patterns, and grinding a backside of the semiconductor wafer, wherein each unique pattern of the k semiconductor devices is composed of a combination of the unique patterns of the first and second repeating patterns, wherein the position of the semiconductor device is identified based on the unique patterns of the first and second repeating patterns and an angle of a grinding mark.

公开(公告)号：US11175321B1

公开(公告)日：2021-11-16

申请号：US16923662

申请日：2020-07-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takehiro Ueda

IPC: G01R19/32 ,  H02M3/155 ,  H02M1/00 ,  H01L29/78

Abstract: Semiconductor device includes an element region in which the semiconductor element is provided, a semiconductor substrate including an outer peripheral region surrounding the element region, a plurality of semiconductor elements provided in an array-like in the element region. The element region includes a main circuit region in which the main circuit of semiconductor device is formed, and a sense circuit region in which a sense circuit for measuring the drain current flowing through the semiconductor element of the main circuit region is formed. Semiconductor element of the sense circuit region is surrounded by other semiconductor elements. Sense circuit region is covered with a main circuit source electrode which is connected to the semiconductor element of the main circuit region.

公开(公告)号：US08610178B2

公开(公告)日：2013-12-17

申请号：US13721962

申请日：2012-12-20

Applicant: Renesas Electronics Corporation

Inventor： Takehiro Ueda

IPC: H01L27/10

CPC classification number: H01L23/5256 ,  H01L23/345 ,  H01L23/525 ,  H01L23/528 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.