Abstract:
An asynchronous pipeline structure includes a plurality of functional blocks comprising dynamic logic, each block precharged to an idle state responsive to a precharge control signal applied thereto, with each block, upon being precharged, receiving input data thereto for processing, and holding output data generated thereby during an evaluate phase, independent of a reset of the input data; for each block, a completion detector circuit coupled to the output of the functional block, the completion detector circuit generating an acknowledgement signal that indicates validity or absence of data at the output of the block; and for each block, a precharge control circuit generating a precharge signal, wherein for a given block, a first input to the precharge control circuit comprises the acknowledgment signal from a downstream completion detector, and second input to the precharge control circuit comprises the precharge signal from an upstream precharge control circuit.
Abstract:
Method and apparatus for tracking pulse trains from one or more emitters. For a valid pulse, PRI parameters are measured. A pulse pattern count is incremented and checked to determine if a track is acquired for the emitter.
Abstract:
A system for beamforming employing true time delay. The system includes a deserializer configured to receive a serial data stream and to convert the serial data stream into a plurality of parallel data streams, a zero-insertion block configured to insert zeroes into each of the parallel data streams, and a crossbar switch having a plurality of inputs and an equal number of outputs. The inputs are connected to the zero-insertion block, each of the outputs corresponding to one of the inputs. The crossbar switch is configured, in a first state, to connect each output to the corresponding input, and in a second state, to connect each output to an input different from the corresponding input, the set of outputs being a circular shift of the set of inputs.
Abstract:
Method and apparatus for tracking pulse trains from one or more emitters. For a valid pulse. PRI parameters are measured. A pulse pattern count is incremented and checked to determine if a track is acquired for the emitter.
Abstract:
Embodiments are directed to receiving an incoming signal, converting, by an analog circuit, the signal to a discrete time signal, applying, by the analog circuit, a transformation algorithm to the discrete time signal to obtain frequency samples of the discrete time signal, applying, by the analog circuit, a cross correlation algorithm to the frequency samples to obtain a cross spectral density (CSD), detecting, by the analog circuit, phase slopes associated with the CSD, and calculating an angle of arrival (AoA) of the incoming signal based on the phase slopes.
Abstract:
A digital signal processing apparatus includes a digital circuit device having one or more elements configured to process digital data; a power supply configured to deliver a controllable operating voltage for the one or more elements; control logic configured to receive feedback signals from each of the one or more elements, the feedback signals indicative of a rate at which data is moving through each individual element; and the control logic configured to output a control signal to the power supply so as to cause the power supply to reduce the operating voltage for the one or more elements responsive to a decreasing workload detected therein, and to cause the power supply to increase the operating voltage for the one or more pipelines responsive to an increasing workload detected therein.
Abstract:
Embodiments are directed to receiving an incoming signal, converting, by an analog circuit, the signal to a discrete time signal, applying, by the analog circuit, a transformation algorithm to the discrete time signal to obtain frequency samples of the discrete time signal, applying, by the analog circuit, a cross correlation algorithm to the frequency samples to obtain a cross spectral density (CSD), detecting, by the analog circuit, phase slopes associated with the CSD, and calculating an angle of arrival (AoA) of the incoming signal based on the phase slopes.
Abstract:
Method and apparatus for generating channelized hardware-independent waveforms include: generating metadata associated with a waveform, the metadata including a frequency list, a phase list and amplitude information, wherein the metadata is generated independent of a number of channels; interpreting the metadata to generate channel select, frequency, phase and amplitude parameters; providing the frequency, phase and amplitude parameters to a direct digital synthesizer (DDS) to generate a digital signal; providing the channel select parameter to a channel selector to generate a plurality of channelized waveforms from the generated digital signal; and transmitting the plurality of channelized waveforms over a plurality of communication channels.
Abstract:
An asymmetric power amplifier includes: an input port for receiving a multi carrier signal including a first subcarrier and a second subcarrier; a first tunable analog filter for filtering the received multi carrier signal into a first signal of the first subcarrier; a second tunable analog filter for filtering the received multi carrier signal into a second signal of the second subcarrier; an amplifier for amplifying the first signal of the first subcarrier; a power amplifier for power amplifying the second signal of the second subcarrier; a combiner for power combining the amplified first signal and the amplified second signal to form a power combined multi carrier signal; and an output port for outputting the power combined multi carrier signal to be transmitted by a transmitter.