Abstract:
A power amplifier structure having: a power divider for dividing power in a signal fed to an input port between a pair of output ports. Each one of a pair of amplifiers has: an input coupled to a corresponding one of the pair of power divider output ports; and an output. A power combiner is provided. Signals at the power divider output ports are fed to the inputs of the pair of amplifiers in a forward direction and then pass through the amplifiers in the forward direction towards the outputs of the pair of amplifiers. Connectors direct the signals at the amplifier outputs to the power combiners, the signal then passing through the power combiner to an output port in a direction opposite to the forward direction.
Abstract:
A branchline coupler structure having a pair of main transmission lines disposed on different horizontal levels of a support structure and a pair of shunt transmission lines, vertically disposed and laterally spaced, and disposed in the support structure. A first one of the pair of shunt transmission lines is coupled between: one region of a first one of the pair of main transmission lines and a first end of a second one of the pair of main transmission line. A second one of the pair of shunt transmission lines is coupled between a second region of the first one of the pair of main transmission lines, laterally spaced from the first region, and a second end of the second one of the main transmission lines.
Abstract:
An RF coupler having: a pair of input ports; a pair of output ports; and a coupling region for coupling: a portion of an input signal at a first one of the input ports to first of the pair of output ports and another portion of the input signal fed to the first one of the input ports a second one of the output ports; and one portion of an input signal fed to a second one of the input ports to the second of the pair of output ports and another portion of the input signals fed to the second one of the input ports to the second one of the output ports. The coupling region comprises a plurality of serially connected, vertically stacked, coupling sections. Each one of a plurality of electrically conductive layers is disposed between a pair of the vertically stacked coupling sections.
Abstract:
A MMIC support and cooling structure having a three-dimensional, thermally conductive support structure having a plurality of surfaces and a circuit having a plurality of heat generating electrical components disposed on a first portion of the surfaces and interconnected by microwave transmission lines disposed on a second portion of the plurality of surfaces of the thermally conductive support structure
Abstract:
A Field Effect Transistor (FET) having a substrate; a plurality of active regions disposed on the substrate; and a laterally extending finger-like control electrode disposed on a portion of a surface of the substrate. The active regions are laterally spaced one from the other successively along the laterally extending finger-like control electrode. The laterally extending finger-like control electrode controls a flow of carriers through each one of the plurality of active regions between a source electrode and a drain electrode.
Abstract:
A microwave transmission line having a coplanar waveguide and a pair of conductive members, each one of the pair of conductive members having a proximal end disposed on a portion of a corresponding one of a pair of ground plane conductors of the coplanar waveguide and a distal end disposed over, and vertically spaced from, a region between a center conductor of the coplanar waveguide and a corresponding one of the pair of ground plane conductors of the coplanar waveguide. The distal ends are laterally separated from each other by a region disposed over the center conductor.
Abstract:
A Field Effect Transistor (FET) having: a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads; a gate contact connected to the gate electrodes of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed on a surface in a two-dimensional array.
Abstract:
A depletion mode FET having a source electrode connected to ground; and a bias circuit for producing a bias current for a gate electrode of the FET. The bias circuit includes a pair of source follower transistors circuits; a first one of the pair of two source follower transistor circuits being coupled between a first voltage supply having a first polarity relative to the ground potential and a second voltage supply having a second polarity relative to ground potential, the first polarity being opposite to the second polarity, the first one of the pair of the source follower transistor circuits supplying a control signal to a second one of the pair of source follower transistor circuits. The second one of the pair of source follower transistors circuits is coupled between the second voltage supply and the ground potential and wherein the second one of the pair of source follower transistor circuits produces a bias signal for the control electrode of the output transistor.
Abstract:
A Field Effect Transistor (FET) having a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads. The FET includes; a gate contact connected to the gate electrode of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed in a loop configuration.
Abstract:
A Field Effect Transistor (FET) having: a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads; a gate contact connected to the gate electrodes of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed on a surface in a two-dimensional array.