公开(公告)号：US20230290387A1

公开(公告)日：2023-09-14

申请号：US17654295

申请日：2022-03-10

Applicant: QUALCOMM Incorporated

Inventor： Pradeep RAJ ,  Rahul SAHU ,  Sharad Kumar GUPTA ,  Hemant PATEL ,  Diwakar SINGH

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/12

CPC classification number: G11C7/1012 ,  G11C7/1096 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/06 ,  G11C7/12

Abstract: One implementation includes a random access memory (RAM) that has a muted multiplexing functionality. For instance, a RAM may be implemented having a first outer bank, a first inner bank, a second outer bank, and a second inner bank, each coupled to a controller. Multiplexing circuits for the outer banks may be disposed adjacent the outer banks and away from the controller, whereas the multiplexing circuits for the inner banks may be disposed within or adjacent to the controller.

公开(公告)号：US20230005556A1

公开(公告)日：2023-01-05

申请号：US17364738

申请日：2021-06-30

Applicant: QUALCOMM Incorporated

Inventor： Rahul SAHU ,  Sharad Kumar GUPTA ,  Jung Pill KIM ,  Chulmin JUNG ,  Jais ABRAHAM

IPC: G11C29/10 ,  G11C7/06 ,  G11C7/10

Abstract: A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.

公开(公告)号：US20220021389A1

公开(公告)日：2022-01-20

申请号：US16930151

申请日：2020-07-15

Applicant: QUALCOMM Incorporated

Inventor： Narender PONNA ,  Sharad Kumar GUPTA ,  Akhtar ALAM

IPC: H03K19/003 ,  H03K19/0185 ,  H03K19/017

Abstract: According to certain aspects, a level shifter includes a first branch including a first pull-up transistor configured to pull up a first node, and a first pull-down transistor configured to pull down the first node. The level shifter also includes a second branch including a second pull-up transistor configured to pull up a second node, and a second pull-down transistor configured to pull down the second node. The level shifter further includes a third branch including a third pull-up transistor configured to pull up a third node, and a third pull-down transistor configured to pull down the third node. The first branch is cross coupled with the third branch, the second branch is cross coupled with the third branch, the first pull-down transistor has a first channel width, the second pull-down transistor has a second channel width, and the first channel width is greater than the second channel width.