公开(公告)号：US20190305077A1

公开(公告)日：2019-10-03

申请号：US15937097

申请日：2018-03-27

Applicant: QUALCOMM Incorporated

Inventor： Peijie FENG ,  Junjing BAO ,  Ye LU ,  Giridhar NALLAPATI

IPC: H01L49/02 ,  H01L23/522

Abstract: A capacitor includes first conductive fingers interdigitated with second conductive fingers at an Mx interconnect level, and third conductive fingers interdigitated with fourth conductive fingers at an Mx-1 interconnect level. The third conductive fingers are offset from the first conductive fingers. The second conductive fingers are offset from the fourth conductive fingers. The capacitor further includes fifth conductive fingers interdigitated with sixth conductive fingers at an Mx-2 interconnect level. The fifth conductive fingers are offset from the third conductive fingers. The sixth conductive fingers are offset from the fourth conductive fingers. The capacitor further includes seventh conductive fingers interdigitated with eighth conductive fingers at an Mx-3 interconnect level. The seventh conductive fingers are offset from the fifth conductive fingers. The eighth conductive fingers are offset from the sixth conductive fingers. A first set of vias electrically couples the first conductive fingers to the fifth conductive fingers.

公开(公告)号：US20220109053A1

公开(公告)日：2022-04-07

申请号：US17061709

申请日：2020-10-02

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Jun YUAN ,  Peijie FENG

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/423

Abstract: Disclosed are optimized contract structures and fabrication techniques thereof. At least one aspect includes a semiconductor die. The semiconductor die includes a substrate and a contact disposed within the substrate. The contact includes a first portion with a first vertical cross-section having a first cross-sectional area. The first vertical cross-section has a first width and a first height. The contact also includes a second portion with a second vertical cross-section having a second cross-sectional area less than the first cross-sectional area. The second vertical cross-section includes a lower portion having the first width and a second height less than the first height, and an upper portion disposed above the lower portion and having a second width less than the first width and having a third height less than the first height.

公开(公告)号：US20220108983A1

公开(公告)日：2022-04-07

申请号：US17061941

申请日：2020-10-02

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Ye LU ,  Chenjie TANG ,  Peijie FENG

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78

Abstract: Certain aspects of the present disclosure relate to a semiconductor device (e.g., a gate-all-around (GAA) semiconductor device) comprising at least one superlattice fin. One example superlattice fin includes a first plurality of nanosheets composed of a first semiconductor material and a second plurality of nanosheets composed of a second semiconductor material, the second semiconductor material being different from the first semiconductor material, wherein a width of a first nanosheet in the first plurality of nanosheets differs from a width of a second nanosheet in the second plurality of nanosheets, the second nanosheet being adjacent to the first nanosheet.

公开(公告)号：US20210028115A1

公开(公告)日：2021-01-28

申请号：US16517845

申请日：2019-07-22

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Peijie FENG ,  Haining YANG ,  Jun YUAN

IPC: H01L23/532 ,  H01L23/535 ,  H01L29/45 ,  H01L21/768

Abstract: Certain aspects of the present disclosure generally relate to an integrated device including a low parasitic middle-of-line (MOL) structure. The integrated device generally includes a plurality of semiconductor devices; an MOL structure disposed above the plurality of semiconductor devices and comprising a dielectric layer; a first barrier-less conductor extending between a first terminal of a semiconductor device in the plurality of semiconductor devices and into the MOL structure; and a first air gap disposed between a lateral surface of an upper portion of the first barrier-less conductor and the dielectric layer of the MOL structure.

公开(公告)号：US20200066858A1

公开(公告)日：2020-02-27

申请号：US16112484

申请日：2018-08-24

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Peijie FENG ,  Ye LU ,  Bin YANG

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/51 ,  H01L29/66

Abstract: A thin film transistor may include an insulating substrate and a layer of semiconductor material disposed over the insulating substrate. The thin film transistor may further include a gate electrode, a source electrode and a drain electrode disposed over the insulating substrate. The thin film transistor may further include a layer of first dielectric material disposed in between the gate electrode and the source and drain electrodes, and a layer of second dielectric material in contact with the layer of first dielectric material. The second dielectric material has a negative index.