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公开(公告)号：US20160357504A1
公开(公告)日：2016-12-08
申请号：US14731499
申请日：2015-06-05
Applicant: QUALCOMM Incorporated
Inventor： Alexander Khazin , Lior Amarilio
CPC classification number: G06F3/165 , G06F1/08 , G06F1/324 , G11B27/3036 , H04R3/00 , H04R2460/03 , Y02D10/126
Abstract: Power reduction through clock management techniques are disclosed. In one aspect, the clock management is applied to a clock signal on a SOUNDWIRE™ communication bus. In particular, a control system associated with a master device on the communication bus may evaluate frequency requirements of audio streams on the communication bus and select a lowest possible clock frequency that meets the frequency requirements. Lower clock frequencies result in fewer clock transitions and result in a net power saving relative to higher clock frequencies. In the event of a clock frequency change, the master device communicates the clock frequency that will be used prospectively to slave devices on the communication bus, and all devices transition to the new frequency at the same frame boundary. In addition to the power savings, exemplary aspects of the present disclosure do not impact an active audio stream.
Abstract translation: 通过时钟管理技术降低功耗。 在一个方面，时钟管理被应用于SOUNDWIRE TM通信总线上的时钟信号。 特别地，与通信总线上的主设备相关联的控制系统可以评估通信总线上的音频流的频率需求，并选择满足频率要求的最低可能时钟频率。 较低的时钟频率导致更少的时钟转换，并导致相对于较高时钟频率的净功率节省。 在时钟频率变化的情况下，主设备将预期使用的时钟频率传送到通信总线上的从设备，并且所有设备在相同帧边界处转换到新频率。 除了功率节省之外，本公开的示例性方面不影响活动音频流。
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公开(公告)号：US11522738B1
公开(公告)日：2022-12-06
申请号：US17354332
申请日：2021-06-22
Applicant: QUALCOMM Incorporated
Inventor： Tomer Rafael Ben-Chen , Sharon Graif , Lior Amarilio
Abstract: High-speed communication links with self-aligned scrambling on a communication link that sends scrambled signals may include a slave device that may self-align by initially detecting an unscrambled preamble symbol and more particularly detect an edge of the unscrambled preamble symbol. Based on the detected edge, a fine alignment adjustment may be made by testing subsequent scrambled data for a repeated pattern such as an IDLE symbol by comparing the repeated pattern to a candidate scrambled sequence that has been received through the communication link. The comparison may use an exclusive OR (XOR) circuit on some bits to derive a scrambler seed that is used to test for a match for the remaining bits. If there is a match, the scrambler seed and frame alignment have been detected and alignment is achieved.
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13.发明授权公开(公告)号：US11360916B2
公开(公告)日：2022-06-14
申请号：US17005143
申请日：2020-08-27
Applicant: QUALCOMM Incorporated
Inventor： Sharon Graif , Navdeep Mer , Lior Amarilio
Abstract: Systems, methods, and apparatus are configured to enable a receiver to provide feedback. A feedback mechanism enables a transmitting device to identify the provider of feedback for a multicast transmission, and the feedback transmitted by one or more individual receivers of the multicast transmission. A method includes receiving a multicast write command from the serial bus in a first datagram, writing a data byte received in a first data frame of the first datagram to a register address identified by the first datagram, and providing device-specific feedback regarding the first datagram in a multibit slot within the second data frame. The multibit slot is one of a plurality of sequential multibit slots defined for the second data frame. Each multibit slot in the plurality of sequential multibit slots may provide device-specific feedback from one receiving device addressed by the multicast write command.
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公开(公告)号：US11064295B2
公开(公告)日：2021-07-13
申请号：US16597902
申请日：2019-10-10
Applicant: QUALCOMM Incorporated
Inventor： Lior Amarilio , Yiftach Benjamini , Sharon Graif
Abstract: Systems and methods for scrambling data-port audio in SOUNDWIRE™ systems include a scramble enable feature that allows a data source to scramble an outgoing channel content with a cyclic linear feedback shift register (LFSR) using a pseudo-random binary sequence (PRBS) such as, but not limited to, the PRBS defined in the SOUNDWIRE specification. Data ports for audio sinks receiving the scrambled content descramble the content for use by the audio sink. In a specific exemplary aspect, an output of the LFSR is added or subtracted with the audio data to make the microphones independent of one another and reduce crosstalk.
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公开(公告)号：US11010327B2
公开(公告)日：2021-05-18
申请号：US16519531
申请日：2019-07-23
Applicant: QUALCOMM Incorporated
Inventor： Sharon Graif , Meital Zangvil , Lior Amarilio
Abstract: Systems, methods, and apparatus are described. A method for data communication performed at a master device includes configuring a serial interface for a point-to-point mode of operation, transmitting a first two-bit command through the serial interface, the two-bit command including a one-bit address and a read/write bit, and initiating a transaction through the serial interface. The transaction may be identified by the two-bit command and is conducted in accordance with an I3C protocol. The transaction may include the transfer of one or more data frames formatted in accordance with the I3C protocol. The method may include receiving an acknowledgement from a slave device in response to the first two-bit command.
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Patent Agency Ranking
公开(公告)号：US10713199B2
公开(公告)日：2020-07-14
申请号：US16012532
申请日：2018-06-19
Applicant: QUALCOMM Incorporated
Inventor： Lior Amarilio , Amit Gil , Sharon Graif
Abstract: System, methods and apparatus are described that can improve available bandwidth on a SoundWire bus without increasing the number of pins used by the SoundWire bus. A method performed at a master device coupled to a SoundWire bus includes providing a clock signal by a first master device over a clock line of a SoundWire bus to a first slave device and a second slave device coupled to the SoundWire bus, transmitting first control information from the first master device to the first slave device over a first data line of the SoundWire bus, and transmitting second control information from the first master device to the second slave device over a second data line of the SoundWire bus. The first control information may be different from the second control information and is transmitted concurrently with the second control information.
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公开(公告)号：US10572439B1
公开(公告)日：2020-02-25
申请号：US16447801
申请日：2019-06-20
Applicant: QUALCOMM Incorporated
Inventor： Sharon Graif , Meital Zangvil , Lior Amarilio
Abstract: Systems, methods, and apparatus are described. An apparatus provides a clock signal, transmits an address on a second line of the serial bus followed by a read/write bit configured to initiate a read transaction, and delays a pulse in the clock signal after transmitting the read/write bit. The pulse may be delayed for a first duration configured to accommodate a latency associated with a first slave device that is a participant in the read transaction. The apparatus may receive an acknowledgement from the first slave device while the pulse is being transmitted and may receive a first data byte from the first slave device after receiving the acknowledgment. The apparatus may stall the clock signal for a second duration after receiving the first data byte from the first slave device, and receive a second data byte from the first slave device after the acknowledgment.
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18.发明申请公开(公告)号：US20190065431A1
公开(公告)日：2019-02-28
申请号：US16056885
申请日：2018-08-07
Applicant: QUALCOMM Incorporated
Inventor： Lior Amarilio , Chulkyu Lee , Harvijaysinh Raj
Abstract: Providing zero-overhead frame synchronization using synchronization strobe polarity for SOUNDWIRE Extension buses is disclosed. In one aspect, a downstream-facing interface (DFI) device determines a polarity of a next synchronization strobe of a bitstream based on a value of a next frame synchronization pattern, and adjusts the next synchronization strobe of the bitstream to comprise a signal transition corresponding to the polarity. The processor-based DFI device then transmits the bitstream containing the next synchronization strobe (e.g., via a SOUNDWIRE Extension bus, such as a SOUNDWIRE-XL or SOUNDWIRE-NEXT bus, to one or more upstream-facing interface (UFI) devices). In another aspect, a processor-based UFI device receives the bitstream, and detects the encoded polarity of the synchronization strobe. The processor-based UFI device reconstructs the frame synchronization pattern based on the polarity of the synchronization strobe, and performs frame synchronization based on the frame synchronization pattern.
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公开(公告)号：US20180260357A1
公开(公告)日：2018-09-13
申请号：US15453678
申请日：2017-03-08
Applicant: QUALCOMM Incorporated
Inventor： Yossi Amon , Lior Amarilio , Ofer Rosenberg
IPC: G06F13/42 , G06F13/364 , G06F13/40
CPC classification number: G06F13/4291 , G06F13/364 , G06F13/404 , G06F2213/0016
Abstract: Systems, methods, and apparatus are described that enable an I3C master device to support I2C clock stretch used by I2C devices connected to an I3C bus. A method performed at a master device includes enabling a line driver to drive a clock wire of the serial bus in accordance with a clock signal and when the master device is configured for a first mode of operation, enabling the line driver to drive the clock wire to a first voltage level when the clock signal is in a first signaling state and when the master device is configured for a second mode of operation, and disabling the line driver when the clock signal is in a second signaling state in the second mode of operation. A resistor pulls the clock wire to a second voltage level when the clock signal is in the second signaling state.
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公开(公告)号：US10003456B2
公开(公告)日：2018-06-19
申请号：US15430134
申请日：2017-02-10
Applicant: QUALCOMM Incorporated
Inventor： Jin-Sheng Wang , Lior Amarilio
IPC: H04L7/04 , G06F13/42 , H04L5/16 , H04L25/493 , H04R3/00
CPC classification number: H04L7/04 , G06F13/4291 , H04L5/16 , H04L25/493 , H04L27/142 , H04R3/00
Abstract: System, methods and apparatus are described that improve link turnaround performance in a differentially driven link. A method performed at a first device coupled to a two-wire serial link includes transmitting from the first device first differentially-encoded data to a second device over the two-wire serial link during a first time period, receiving at the first device second differentially-encoded data from the second device over the two-wire serial link during a second time period, and driving by the first device both wires of the two-wire serial link to a common voltage level during a third time period, the third time period spanning a link turnaround period between the first time period and the second time period. Both wires of the two-wire serial link are driven toward the common voltage level by the second device during the third time period.
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