公开(公告)号：US11349445B2

公开(公告)日：2022-05-31

申请号：US17017239

申请日：2020-09-10

Applicant: QUALCOMM Incorporated

Inventor： Ying Duan ,  Jing Wu ,  Zhi Zhu

IPC: H03K3/037 ,  H03F3/45 ,  H03K5/24 ,  H04L25/03 ,  H03K5/00

Abstract: A receiver including a first differential sense amplifier configured to amplify an input differential data signal to generate an output differential data signal; a first set of one or more differential decision feedback equalizer (DFE) taps configured to modify the output differential data signal based on a set of one or more differential tap signals, wherein the first set of one or more differential DFE taps affect an output common mode voltage associated with the output differential data signal; and a compensation circuit configured to adjusts the output common mode voltage to compensate for the effect on the output common mode voltage by the set of one or more differential DFE taps. The compensation circuit includes reference and replica receivers to generate reference and replica output common mode voltages, and a feedback circuit to adjust the output common mode voltage based on the reference and replica output common mode voltages.

公开(公告)号：US10706494B2

公开(公告)日：2020-07-07

申请号：US16103336

申请日：2018-08-14

Applicant: QUALCOMM Incorporated

Inventor： Andrew Evan Gruber ,  Pramod Vasant Argade ,  Jing Wu

IPC: G06T1/20 ,  G06T5/00 ,  G06F9/30 ,  G06F9/38

Abstract: A method for processing data in a graphics processing unit including receiving an indication that all threads of a warp in a graphics processing unit (GPU) are to execute a same branch in a first set of instructions, storing one or more predicate bits in a memory as a single set of predicate bits, wherein the single set of predicate bits applies to all of the threads in the warp, and executing a portion of the first set of instructions in accordance with the single set of predicate bits. Executing the first set of instructions may include executing the first set of instruction in accordance with the single set of predicate bits using a single instruction, multiple data (SIMD) processing core and/or executing the first set of instruction in accordance with the single set of predicate bits using a scalar processing unit.

公开(公告)号：US20190050958A1

公开(公告)日：2019-02-14

申请号：US16103336

申请日：2018-08-14

Applicant: QUALCOMM Incorporated

Inventor： Andrew Evan Gruber ,  Pramod Vasant Argade ,  Jing Wu

IPC: G06T1/20 ,  G06F9/38 ,  G06T5/00 ,  G06F9/30

Abstract: A method for processing data in a graphics processing unit including receiving an indication that all threads of a warp in a graphics processing unit (GPU) are to execute a same branch in a first set of instructions, storing one or more predicate bits in a memory as a single set of predicate bits, wherein the single set of predicate bits applies to all of the threads in the warp, and executing a portion of the first set of instructions in accordance with the single set of predicate bits. Executing the first set of instructions may include executing the first set of instruction in accordance with the single set of predicate bits using a single instruction, multiple data (SIMD) processing core and/or executing the first set of instruction in accordance with the single set of predicate bits using a scalar processing unit.

公开(公告)号：US10558460B2

公开(公告)日：2020-02-11

申请号：US15379195

申请日：2016-12-14

Applicant: QUALCOMM Incorporated

Inventor： Yun Du ,  Liang Han ,  Lin Chen ,  Chihong Zhang ,  Hongjiang Shang ,  Jing Wu ,  Zilin Ying ,  Chun Yu ,  Guofang Jiao ,  Andrew Gruber ,  Eric Demers

IPC: G06F9/30 ,  G06F9/38 ,  G06T1/20 ,  G06F8/41

Abstract: Systems and techniques are disclosed for general purpose register dynamic allocation based on latency associated with of instructions in processor threads. A streaming processor can include a general purpose registers configured to stored data associated with threads, and a thread scheduler configured to receive allocation information for the general purpose registers, the information describing general purpose registers that are to be assigned as persistent general purpose registers (pGPRs) and volatile general purpose registers (vGPRs). The plurality of general purpose registers can be allocated according to the received information. The streaming processor can include the general purpose registers allocated according to the received information, the allocated based on execution latencies of instructions included in the threads.