公开(公告)号：US11164610B1

公开(公告)日：2021-11-02

申请号：US16894606

申请日：2020-06-05

Applicant: QUALCOMM Incorporated

Inventor： Anil Chowdary Kota ,  Hochul Lee

IPC: G11C7/02 ,  G11C7/06 ,  G11C7/12 ,  G11C7/10 ,  G11C7/14 ,  G11C7/18

Abstract: A memory device with built-in flexible redundancy is provided according to various aspects of the present disclosure. In certain aspects, a memory device includes a first sense amplifier, a second sense amplifier, a first comparator, a second comparator, a reference circuit, and a logic gate. During a redundant read operation, the first sense amplifier, the first comparator, and the reference circuit are used to read one copy of a redundant bit stored in the memory device, and the second sense amplifier, the second comparator, and the reference circuit are used to read another copy of the redundant bit stored in the memory device. The logic gate may then determine a bit value based on the bit values of the read copies of the redundant bit (e.g., determine a bit value of one if the bit value of at least one of the read copies of the redundant bit is one).

公开(公告)号：US11152038B2

公开(公告)日：2021-10-19

申请号：US16792636

申请日：2020-02-17

Applicant: QUALCOMM Incorporated

Inventor： Anil Chowdary Kota ,  Keejong Kim ,  Hochul Lee

IPC: G11C7/10 ,  G11C7/06 ,  G11C17/16 ,  G11C29/14

Abstract: Certain aspects of the present disclosure provide methods and apparatus for testing a one-time programmable (OTP) memory device, including the functionality of a sense amplifier circuit. The OTP memory device includes a memory array, an input latch circuit, and a sense amplifier circuit comprising a current source and a multiplexer. The multiplexer has a first input coupled to an output of the memory array, a second input coupled to the input latch circuit, and an output coupled to an input of the current source circuit.

公开(公告)号：US12094528B2

公开(公告)日：2024-09-17

申请号：US17833852

申请日：2022-06-06

Applicant: QUALCOMM Incorporated

Inventor： Dhvani Sheth ,  Hochul Lee ,  Anil Chowdary Kota ,  Chulmin Jung

IPC: G11C29/14 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C11/418

Abstract: A memory is provided with a plurality of column groups and two redundant column groups. If there are two defective columns in the plurality of column groups, the plurality of column groups may be divided into a no-shift region, a one-shift region, and a two-shift region. The memory includes a plurality of input/output circuits corresponding to the plurality of column groups. Each input/output circuit may provide a data input signal during a write operation and receive a data output signal during a read operation. Each input/output circuit also includes a switch matrix. In the no-shift region, the switch matrix couples the input/output circuit to a core in the corresponding column group. In the one-shift region, the switch matrix couples the input/output circuit to a core in a subsequent column group. In the two-shift region, the switch matrix couples the input/output circuit to a core in a next-to-subsequent column group.

公开(公告)号：US11640835B2

公开(公告)日：2023-05-02

申请号：US17472307

申请日：2021-09-10

Applicant: QUALCOMM Incorporated

Inventor： Anil Chowdary Kota ,  Hochul Lee

IPC: G11C7/02 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/14 ,  G11C7/18

Abstract: A memory device with built-in flexible redundancy is provided according to various aspects of the present disclosure. In certain aspects, a memory device includes a first sense amplifier, a second sense amplifier, a first comparator, a second comparator, a reference circuit, and a logic gate. During a redundant read operation, the first sense amplifier, the first comparator, and the reference circuit are used to read one copy of a redundant bit stored in the memory device, and the second sense amplifier, the second comparator, and the reference circuit are used to read another copy of the redundant bit stored in the memory device. The logic gate may then determine a bit value based on the bit values of the read copies of the redundant bit (e.g., determine a bit value of one if the bit value of at least one of the read copies of the redundant bit is one).

公开(公告)号：US11177010B1

公开(公告)日：2021-11-16

申请号：US16927818

申请日：2020-07-13

Applicant: QUALCOMM Incorporated

Inventor： Hochul Lee ,  Anil Chowdary Kota ,  Anne Srikanth

IPC: G11C17/16 ,  G11C17/18 ,  G11C7/06 ,  G11C7/22 ,  G11C7/12

Abstract: The present disclosure provides bit cells with data redundancy according to various aspects. In certain aspects, a bit cell includes a first memory element coupled to a write bit line, and a first write-access switch coupled between the first memory element and a ground. The bit cell also includes a second memory element coupled to the write bit line, and a second write-access switch coupled between the second memory element and the ground. The bit cell further includes a read-access switch coupled between the first memory element and a read bit line, wherein a control input of the read-access switch is coupled to a read-select line.