公开(公告)号：US20240061795A1

公开(公告)日：2024-02-22

申请号：US17821399

申请日：2022-08-22

Applicant: QUALCOMM Incorporated

Inventor： Ravindranath DODDI ,  Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA

IPC: G06F13/16

CPC classification number: G06F13/1694 ,  G06F2213/0026

Abstract: Various embodiments include methods and devices for implementing a Peripheral Component Interconnect Express (PCIe) link state transition by a computing device. Embodiments may include comprising retrieving, by a PCIe controller, PCIe link configuration data from a memory for a PCIe link in a fast recovery low power state of a link training status and state machine (LTSSM), and re-initializing, by the PCIe controller, the PCIe link using the PCIe link configuration data retrieved from the memory. Embodiments may further include maintaining the PCIe link configuration data in the memory for the PCIe link in the fast recovery low power state of the LTSSM by providing auxiliary power to PCIe configuration registers for the PCIe controller.

公开(公告)号：US20250086132A1

公开(公告)日：2025-03-13

申请号：US18463852

申请日：2023-09-08

Applicant: QUALCOMM Incorporated

Inventor： Prakhar SRIVASTAVA ,  Santhosh Reddy AKAVARAM ,  Aditya Singh PATEL ,  Ravi Kumar SEPURI

IPC: G06F13/40

Abstract: The disclosed techniques store certain information of functional modules and lanes to optimize a die-to-die interconnect link. Based on the information, the apparatus can optimize a link width and a multi-module link configuration of the interconnect link. An integrated circuit device includes a first die, a second die, and a die-to-die (D2D) interconnect link connected between the first die and the second die. The D2D interconnect link includes a plurality of lanes grouped into a plurality of modules. The apparatus maintains a training result of the D2D interconnect link based on the training of the D2D interconnect link, the training result including one or more link configurations of the plurality of modules. The apparatus selects a link configuration of the one or more link configurations to configure the D2D interconnect link including one or more of the plurality of modules.

公开(公告)号：US20240427710A1

公开(公告)日：2024-12-26

申请号：US18339904

申请日：2023-06-22

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA ,  Ravindranath DODDI ,  Rajendra Varma PUSAPATI ,  Sonali JABREVA

IPC: G06F13/16

Abstract: Various embodiments include methods and devices for implementing a Peripheral Component Interconnect Express (PCIe) link configuration by a computing device. Embodiments may include selecting, by a PCIe device, a predetermined PCIe link speed based on a PCIe link configuration mode of a PCIe system of a plurality of PCIe link configuration modes of the PCIe system, and selecting, by the PCIe device, a PCIe link width of one lane for configuring the PCIe link. Embodiments may include selecting a PCIe link speed level lower than a current PCIe link speed in response to a reliability indicator exceeding a reliability threshold for a first PCIe link configuration mode. Embodiments may include selecting a maximum PCIe link speed for the PCIe link for a second PCIe link configuration mode. Embodiments may include increasing the PCIe link width in response to a requested bandwidth exceeding a configuration bandwidth of the PCIe link.

公开(公告)号：US20240402923A1

公开(公告)日：2024-12-05

申请号：US18327691

申请日：2023-06-01

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA ,  Sridhar ANUMALA ,  Hung VUONG ,  Sonali JABREVA ,  Khushboo KUMARI

IPC: G06F3/06

Abstract: Aspects of the present disclosure are directed to techniques and procedures for storing data in a data storage device that uses nonvolatile memory (NVM) to store data. The NVM can be organized into logical units that are assigned respective logical unit numbers. The data storage device can report to a host the amount of spare blocks needed for one or more logical units (LUs), and then the host can relinquish some memory blocks to be reallocated as spare blocks. The data storage device can implement a spare block resource management policy per LU and allocate a predetermined amount of spare blocks per LU. The data storage device can implement a spare block resource management policy per memory type and allocate a predetermined amount of spare blocks for LUs with the same memory type.

公开(公告)号：US20240319913A1

公开(公告)日：2024-09-26

申请号：US18189141

申请日：2023-03-23

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy AKAVARAM ,  Sonali JABREVA ,  Prakhar SRIVASTAVA ,  Surendra PARAVADA ,  Yogananda Rao CHILLARIGA ,  Madhu Yashwanth BOENAPALLI

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0604

Abstract: Aspects of the present disclosure provide various techniques, apparatuses, and methods that can improve the write throughout of a data storage device. In some aspects, the storage device can be provided with multiple write buffers to improve write throughput. In some aspects, the data storage device can continue to handle commands using a command queue while performing a write buffer flush operation. Therefore, the data storage device can avoid suspending the write buffer flush operation when a new command is received by the command queue. In some aspects, the storage device can perform a write buffer flush operation when a command queue is not empty.

公开(公告)号：US20240111354A1

公开(公告)日：2024-04-04

申请号：US17959996

申请日：2022-10-04

Applicant: QUALCOMM Incorporated

Inventor： Prakhar SRIVASTAVA ,  Santhosh Reddy AKAVARAM ,  Ravindranath DODDI ,  Ravi Kumar SEPURI

IPC: G06F1/3234 ,  G06F13/42

CPC classification number: G06F1/3278 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A new peripheral component interconnect express (PCIe) link state can enhance power saving capabilities of a PCIe link operating in a flow control unit (FLIT) mode. A device can operate a data link with a host in a FLIT mode using fixed-sized packets, the data link being in a partial width link state (PLS) in which a first set of lanes of the data link are in an electrical idle state and a second set of lanes of the data link are in an active state available for data traffic with the host. The device can transition one or more lines of the second set of lanes from the PLS to a partial width standby link state (PSLS) in which the one or more lines of the second set of lanes are in a standby state that has lower power consumption than the active state.

公开(公告)号：US20250117144A1

公开(公告)日：2025-04-10

申请号：US18481616

申请日：2023-10-05

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy AKAVARAM ,  Chintalapati BHARATH SAI VARMA ,  Prakhar SRIVASTAVA ,  Sai Jitendra Varma GADIRAJU

IPC: G06F3/06

Abstract: A host device includes a host controller interface (HCI) configured to be coupled to a flash memory device (FMD). The HCI is configured to obtain an indication that a size of a particular write buffer (WB) of the FMD is to be increased. The FMD includes a plurality of memory resources that include a plurality of logical units (LUs) and at least the particular WB. The HCI is also configured to select a particular memory resource for write buffer reallocation based at least in part on a particular usage metric of the particular memory resource.

公开(公告)号：US20250085861A1

公开(公告)日：2025-03-13

申请号：US18464874

申请日：2023-09-11

Applicant: QUALCOMM INCORPORATED

Inventor： Santhosh Reddy AKAVARAM ,  Chintalapati BHARATH SAI VARMA ,  Prakhar SRIVASTAVA ,  Sri Ananda Sai JANNABHATLA ,  Reddy Vijay GUDI

IPC: G06F3/06 ,  G06F12/10

Abstract: Systems and methods improve write performance of a UFS device comprising N logical units (LUNs) and N write buffers (WBs), where N is a positive integer. Each WB is mapped to a respective LUN. Each WB has a respective WB lifetime estimate value and a respective WB lifetime threshold (TH) value. A determination is made as to whether the WB lifetime estimate value associated with at least a first WB of the N WBs is equal to or is greater than the respective WB TH value, and if so, the first WB is remapped to a second LUN of the N LUNs and a second WB of the N WBs is remapped to the first LUN. The remapping is based at least in part on the WB lifetime estimate value associated with the second WB indicating that the second WB has more lifetime remaining than the first WB.

公开(公告)号：US20250077355A1

公开(公告)日：2025-03-06

申请号：US18461287

申请日：2023-09-05

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA ,  Aditya Singh PATEL ,  Yogananda Rao CHILLARIGA

IPC: G06F11/14

Abstract: Aspects of the disclosure provides various systems, apparatuses, and techniques for reducing latencies and power consumption of link training or retraining. In some aspects, the techniques use a specific register to identify the cause of link retraining. Based on the identified reasons of link retraining, the apparatus can selectively skip the initialization of certain redundant lanes of the link. In some aspects, the Universal Chiplet Interconnect Express (UCIe) Link Training and Status State Machine (LTSSM) can be configured to identify whether link retraining is initiated as part of a trainerror or linkerror exit or not. A UCIe device can have a redundant_recovery (RR) register that can be set to different values to identify the cause of link retraining (e.g., due to trainerror/linkerror or not).

公开(公告)号：US20250044982A1

公开(公告)日：2025-02-06

申请号：US18364277

申请日：2023-08-02

Applicant: QUALCOMM Incorporated

Inventor： Sai Naresh GAJAPAKA ,  Chintalapati BHARATH SAI VARMA ,  Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA ,  Vamsi Krishna SAMBANGI

IPC: G06F3/06

Abstract: Aspects relate to interrupting memory access during background operations of a memory device. In one example a memory device includes a memory controller to initiate a write buffer flush operation. A bus interface is coupled to a main memory and to a write buffer to receive a write command from a host during the write buffer flush operation. The memory controller initiates the write buffer flush operation, suspends the write buffer flush operation in response to the write command, sends a last flushed address of the write buffer from the memory device to the host through the bus interface, and unmaps a portion of the write buffer using the last flushed address.