公开(公告)号：US09897651B2

公开(公告)日：2018-02-20

申请号：US15059341

申请日：2016-03-03

Applicant: QUALCOMM Incorporated

Inventor： Virendra Bansal ,  Rahul Gulati ,  Palkesh Jain ,  Roberto Avanzi

IPC: G01R31/317 ,  G06F1/04 ,  H03K3/037 ,  H03K5/14 ,  G01R31/319 ,  H03K5/00

CPC classification number: G01R31/31727 ,  G01R31/31922 ,  G06F1/04 ,  H03K3/037 ,  H03K5/14 ,  H03K2005/00058

Abstract: Various aspects include a clock monitoring unit/component that is configured to repeatedly/continuously monitor a clock with the speed required to support automobile automation systems without the use of a reference clock. The clock monitoring unit/component may be configured to identify, report, and/or respond to variations or abnormalities in the monitored clock, and initiate an action to prevent the variation from causing or resulting in a failure or a vulnerability to attack. The clock monitoring unit/component in the various aspects may be configured, organized, or arranged to operate so that the circuit is immune or resistant to manipulation, modification, tampering, hacks, and other attacks.

公开(公告)号：US20170357557A1

公开(公告)日：2017-12-14

申请号：US15176745

申请日：2016-06-08

Applicant: QUALCOMM Incorporated

Inventor： Palkesh Jain ,  Virendra Bansal ,  Rahul Gulati

IPC: G06F11/16

CPC classification number: G06F11/1608 ,  G06F11/1604 ,  G06F11/1641 ,  G06F11/184 ,  G06F11/187 ,  G06F2201/805 ,  G06F2201/82

Abstract: The disclosure relates to an apparatus and method for false pass detection in lockstep dual processing core systems, triple modular redundancy (TMR) systems, or other redundant processing systems. A false pass occurs when two processing cores generate matching data outputs, both of which are in error. A false pass may occur when the processing core are both subjected to substantially the same adverse condition, such as a supply voltage drop or a sudden temperature change or gradient. The apparatus includes processing cores configured to generate first and second data outputs and first and second timing violation signals. A voter-comparator validates the first and second data outputs if they match and the first and second timing violation signals indicate no timing violations. Otherwise, the voter comparator invalidates the first and second data outputs. Validated data outputs are used for performing additional operations, and invalidated data outputs may be discarded.

公开(公告)号：US20170255223A1

公开(公告)日：2017-09-07

申请号：US15059341

申请日：2016-03-03

Applicant: QUALCOMM Incorporated

Inventor： Virendra Bansal ,  Rahul Gulati ,  Palkesh Jain ,  Roberto Avanzi

IPC: G06F1/04 ,  H03K5/14 ,  H03K3/037

CPC classification number: G01R31/31727 ,  G01R31/31922 ,  G06F1/04 ,  H03K3/037 ,  H03K5/14 ,  H03K2005/00058

Abstract: Various aspects include a clock monitoring unit/component that is configured to repeatedly/continuously monitor a clock with the speed required to support automobile automation systems without the use of a reference clock. The clock monitoring unit/component may be configured to identify, report, and/or respond to variations or abnormalities in the monitored clock, and initiate an action to prevent the variation from causing or resulting in a failure or a vulnerability to attack. The clock monitoring unit/component in the various aspects may be configured, organized, or arranged to operate so that the circuit is immune or resistant to manipulation, modification, tampering, hacks, and other attacks.

公开(公告)号：US11424621B2

公开(公告)日：2022-08-23

申请号：US16774023

申请日：2020-01-28

Applicant: QUALCOMM Incorporated

Inventor： Palkesh Jain ,  Rahul Gulati

IPC: H02J4/00 ,  G06F1/18 ,  G06F1/3203 ,  H01L23/525 ,  H01L27/08 ,  H02J9/00

Abstract: In certain aspects, a device comprises a first processing unit; a first power distribution network coupled to the first processing unit; a first decoupling capacitor coupled to the first power distribution network; a second processing unit configured to be identical to the first processing unit; a second power distribution network coupled to the second processing unit; and a second decoupling capacitor coupled to the second power distribution network, wherein the second decoupling capacitor is configured to have different effect on the second power distribution network than the first decoupling capacitor on the first power distribution network.

公开(公告)号：US11416049B2

公开(公告)日：2022-08-16

申请号：US16826729

申请日：2020-03-23

Applicant: QUALCOMM Incorporated

Inventor： Palkesh Jain ,  Rahul Gulati

IPC: G01R31/317 ,  G06F1/20 ,  G06F1/3203

Abstract: Various embodiments may include methods and systems for monitoring characteristics of a system-on-a-chip. Various embodiments may include inputting, from a test data input connection, test data to a first scan chain section including a first group of logic gates located within a first region of the SoC. Various embodiments may include providing, from a first clock gate associated with the first region of the SoC, a clock signal to the first group of logic gates. Various embodiments may include measuring, using a first sensor, the characteristics at a second region of the SoC in response to providing the clock signal to the first group of logic gates. Embodiments may further include processing or analyzing measured characteristics to determine a testing result.

公开(公告)号：US10141297B1

公开(公告)日：2018-11-27

申请号：US15830173

申请日：2017-12-04

Applicant: QUALCOMM Incorporated

Inventor： Palkesh Jain ,  Mehdi Saeidi ,  Jon James Anderson ,  Chethan Swamynathan ,  Richard Wunderlich

IPC: H01L27/02 ,  G06F17/50

Abstract: An integrated device that includes a substrate, a device level layer formed over the substrate, and interconnect portion over the device level layer. The device level layer includes a plurality of first device level cells, each first device level cell comprising a first configuration. The device level layer includes a plurality of second device level cells. At least one second device level cell includes a second configuration that is different than the first configuration. The plurality of second device level cells is located over at least one region of the integrated device comprising at least one hotspot.

公开(公告)号：US10089194B2

公开(公告)日：2018-10-02

申请号：US15176745

申请日：2016-06-08

Applicant: QUALCOMM Incorporated

Inventor： Palkesh Jain ,  Virendra Bansal ,  Rahul Gulati

IPC: G06F11/00 ,  G06F11/16 ,  G06F11/18

Abstract: The disclosure relates to an apparatus and method for false pass detection in lockstep dual processing core systems, triple modular redundancy (TMR) systems, or other redundant processing systems. A false pass occurs when two processing cores generate matching data outputs, both of which are in error. A false pass may occur when the processing core are both subjected to substantially the same adverse condition, such as a supply voltage drop or a sudden temperature change or gradient. The apparatus includes processing cores configured to generate first and second data outputs and first and second timing violation signals. A voter-comparator validates the first and second data outputs if they match and the first and second timing violation signals indicate no timing violations. Otherwise, the voter comparator invalidates the first and second data outputs. Validated data outputs are used for performing additional operations, and invalidated data outputs may be discarded.