公开(公告)号：US11320855B1

公开(公告)日：2022-05-03

申请号：US17131909

申请日：2020-12-23

Applicant: QUALCOMM INCORPORATED

Inventor： Naveen Kumar Narala ,  Matthew Severson

IPC: G06F1/12

Abstract: Debug time stamp counters in a computing device may be synchronized based on signals indicating awakening of a component of the computing device from a sleep state. A count from a global counter in a first component may be loaded into a replica global counter in a second component. The count from the global counter may be loaded into a first debug time stamp counter in the first component in response to a first preload signal indicating awakening of the first component from a sleep state or in response to a second preload signal indicating awakening of the second component from a sleep state. The count from the replica global counter may be loaded into a second debug time stamp counter in the second component in response to the second preload signal.

公开(公告)号：US11132208B2

公开(公告)日：2021-09-28

申请号：US16689666

申请日：2019-11-20

Applicant: QUALCOMM Incorporated

Inventor： Matthew Severson ,  Kangmin Lee ,  Cristian Duroiu ,  Simon Peter William Booth ,  Steven Halter

IPC: G06F9/44 ,  G06F1/04 ,  G06F9/445

Abstract: In some aspects, the present disclosure provides a method for bandgap voting. In some configurations, the method includes receiving: (i) a first set of votes from a first client of a system, and (ii) a second set of votes from a second client of the system, wherein the first set of votes indicate a first desired set of operational parameters for controlling a plurality of physical resources in the system, wherein the second set of votes indicate a second desired set of operational parameters for controlling the plurality of physical resources, and wherein the plurality of physical resources are shared by the first client and the second client.

公开(公告)号：US12235699B2

公开(公告)日：2025-02-25

申请号：US18166381

申请日：2023-02-08

Applicant: QUALCOMM Incorporated

Inventor： Vijayakumar Ashok Dibbad ,  Nikhil Ashok Bhelave ,  Jeffrey Gemar ,  Matthew Severson

IPC: G06F1/30

Abstract: Various embodiments include methods performed by a processor for managing voltage droop margins of a power distribution network (PDN). Various embodiments may include receiving, by a processor from a first client powered by a shared power rail within the PDN, a first requested performance corner, receiving, by the processor from a second client powered by the shared power rail, a second requested performance corner, determining by the processor a first peak current value based on the first requested performance corner, determining by the processor a second peak current value based on the second requested performance corner, determining by the processor a system voltage droop margin based on the first peak current value, the second peak current value, and an impedance value of the PDN, and adjusting a voltage of the shared power rail based on the system voltage droop margin.

公开(公告)号：US12182036B2

公开(公告)日：2024-12-31

申请号：US18163446

申请日：2023-02-02

Applicant: QUALCOMM Incorporated

Inventor： George Patsilaras ,  Engin Ipek ,  Goran Goran ,  Hamza Omar ,  Bohuslav Rychlik ,  Jeffrey Gemar ,  Matthew Severson ,  Andrew Edmund Turner

IPC: G06F12/126 ,  G06F12/0888

Abstract: Providing content-aware cache replacement and insertion policies in processor-based devices is disclosed. In some aspects, a processor-based device comprises a cache memory device and a cache controller circuit of the cache memory device. The cache controller circuit is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device, based on a plurality of bit values of each of the plurality of cached data values. The cache controller circuit is configured to identify, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The cache controller circuit is also configured to evict the target cached data value from the cache memory device.

公开(公告)号：US11829168B2

公开(公告)日：2023-11-28

申请号：US17088066

申请日：2020-11-03

Applicant: QUALCOMM Incorporated

Inventor： Matthew Severson ,  Timothy Zoley ,  Lipeng Cao ,  Kevin Bradley Citterelle ,  Richard Gerard Hofmann

IPC: G05F1/46 ,  G01K7/18 ,  G01R19/00 ,  G06F1/3206 ,  G06F1/324 ,  H05K1/18 ,  H05K1/16 ,  G01K7/42 ,  G06F1/3296 ,  G01R19/32 ,  G01R1/20 ,  G01R19/165 ,  G01R19/25 ,  G06F15/78 ,  G06N5/04

CPC classification number: G05F1/46 ,  G01K7/18 ,  G01R19/0092 ,  G06F1/324 ,  G06F1/3206 ,  H05K1/181 ,  H05K2201/10151

Abstract: An apparatus including a printed circuit board (PCB) including a sense resistor; and an integrated circuit (IC) mounted on the PCB, wherein at least a portion of the IC draws current from a power rail, wherein the sense resistor is coupled between the power rail and the IC, wherein the sense resistor is configured to produce a sense voltage in response to the current drawn by the at least portion of the IC, and wherein the IC includes a current sensor configured to generate a signal indicative of the current drawn by the at least portion of the IC based on the sense voltage.

公开(公告)号：US20230046542A1

公开(公告)日：2023-02-16

申请号：US17402884

申请日：2021-08-16

Applicant: QUALCOMM Incorporated

Inventor： Naveen Kumar NARALA ,  Matthew Severson ,  Haobo Zhao

IPC: G06F1/12 ,  G06F1/10 ,  G06F1/3206 ,  G06F13/20

Abstract: Various embodiments include methods and systems for providing sleep clock edge-based global counter synchronization in a multiple-chiplet system. A system-on-a-chip (SoC) may include a first chiplet including a first chiplet global counter subsystem, and a second chiplet including a second chiplet global counter subsystem. The SoC may further include an interface bus communicatively coupling the first chiplet and the second chiplet, and a power management integrated circuit (PMIC) configured to supply a sleep clock to the first chiplet and the second chiplet. The first chiplet may be configured to transmit a global counter synchronization pulse trigger to the second chiplet across the interface bus. The second chiplet may be configured to load a global counter synchronization value into the second chiplet global counter subsystem at a sleep clock synchronization edge of the sleep clock in response to receiving the global counter synchronization pulse trigger.

公开(公告)号：US11449125B1

公开(公告)日：2022-09-20

申请号：US17220603

申请日：2021-04-01

Applicant: QUALCOMM INCORPORATED

Inventor： Colin Beaton Verrilli ,  Matthew Severson

IPC: G06F1/00 ,  G06F1/3287 ,  G01R21/133 ,  G06F1/3296 ,  G06F1/324

Abstract: In each of two or more pipelined subsystems, the relative amount of time that the processing cores are idle may be determined. If the idle ratio is below a threshold, the clock frequency and voltage may be adjusted using dynamic clock and voltage scaling (DCVS) based on a power limit. However, if the idle ratio exceeds the threshold, the clock frequency and voltage may be decreased without regard to the power limit.