公开(公告)号：US12164460B2

公开(公告)日：2024-12-10

申请号：US17923110

申请日：2021-04-16

Applicant: QUALCOMM Incorporated

Inventor： Sharon Graif ,  Navdeep Mer ,  Naveen Kumar Narala ,  Sriharsha Chakka

IPC: G06F13/42 ,  G06F13/40

Abstract: Systems, methods, and apparatus are configured to enable a receiver to provide feedback. In one example, a method performed at a device coupled to a serial bus includes receiving a write command from the serial bus in a datagram, writing a data byte received in a first data frame of the datagram to a register address identified by the datagram, and using a second data frame of the datagram to provide feedback regarding the datagram. Feedback may be provided by driving a data line of the serial bus to provide a negative acknowledgement during the second data frame when a transmission error is detected in the datagram, and refraining from driving the data line of the serial bus during the second data frame when no transmission error is detected in the datagram, thereby providing an acknowledgement of the datagram.

公开(公告)号：US11625064B2

公开(公告)日：2023-04-11

申请号：US17402884

申请日：2021-08-16

Applicant: QUALCOMM Incorporated

Inventor： Naveen Kumar Narala ,  Matthew Severson ,  Haobo Zhao

IPC: G06F1/12 ,  G06F1/10 ,  G06F1/32 ,  G06F1/3206

Abstract: Various embodiments include methods and systems for providing sleep clock edge-based global counter synchronization in a multiple-chiplet system. A system-on-a-chip (SoC) may include a first chiplet including a first chiplet global counter subsystem, and a second chiplet including a second chiplet global counter subsystem. The SoC may further include an interface bus communicatively coupling the first chiplet and the second chiplet, and a power management integrated circuit (PMIC) configured to supply a sleep clock to the first chiplet and the second chiplet. The first chiplet may be configured to transmit a global counter synchronization pulse trigger to the second chiplet across the interface bus. The second chiplet may be configured to load a global counter synchronization value into the second chiplet global counter subsystem at a sleep clock synchronization edge of the sleep clock in response to receiving the global counter synchronization pulse trigger.

公开(公告)号：US20220100248A1

公开(公告)日：2022-03-31

申请号：US17037984

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Naveen Kumar Narala ,  Richard Dominic Wietfeldt ,  Christopher Kong Yee Chun

IPC: G06F1/28 ,  G06F13/36

Abstract: Expanded function datagrams in a system power management interface (SPMI) system allow a slave to use an expanded function datagram to address a larger number of masters (e.g., more than four) associated with the SPMI system. Furthermore, addressing may allow for a datagram to be broadcast to multiple masters concurrently. Still further, by signaling that the master addressing is other than the standard SPMI format, the nature of the address and payload of a datagram may be varied to handle larger volumes of data than the SPMI standard normally allows.

公开(公告)号：US11275701B2

公开(公告)日：2022-03-15

申请号：US16910194

申请日：2020-06-24

Applicant: QUALCOMM Incorporated

Inventor： Naveen Kumar Narala

IPC: G06F13/00 ,  G06F12/00 ,  G06F13/16 ,  G06F9/32 ,  G06F13/372 ,  G06F9/30

Abstract: Various embodiments include methods and systems performed by a processor of a first function block for providing secure timer synchronization with a second function block. Various embodiments may include storing, in a shared register space, a first time counter value in which the first time counter value is based on a global counter of the second function block, transmitting, from the shared register space, the stored first time counter value to a preload register of the first function block, receiving, by the first function block, a strobe signal from the second function block configured to enable the first time counter value in the preload register to be loaded into a global counter of the first function block, and configuring the global counter with the first time counter value from the preload register.

公开(公告)号：US11366508B1

公开(公告)日：2022-06-21

申请号：US17180071

申请日：2021-02-19

Applicant: QUALCOMM Incorporated

Inventor： Prashanth Kumar Kakkireni ,  Naveen Kumar Narala ,  Sharon Graif

IPC: G06F1/3234 ,  G06F13/42 ,  G06F1/12 ,  G06F1/3206 ,  G06F1/26

Abstract: Systems, methods, and apparatus for power management are disclosed. A power management integrated circuit has a bus interface circuit configured to couple the power management integrated circuit to a shared communication bus, one or more regulator circuits configured to provide current to a managed device, and a controller. The controller is configured to determine that current consumption by the managed device exceeds a threshold level, generate an extended current level message to be transmitted over the shared communication bus to the managed device and transmit a time value with the extended current level message, the time value indicative of an elapsed time between generation of the extended current level message and start of transmission of the extended current level message.

公开(公告)号：US11334134B2

公开(公告)日：2022-05-17

申请号：US17037984

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Naveen Kumar Narala ,  Richard Dominic Wietfeldt ,  Christopher Kong Yee Chun

IPC: G06F1/28 ,  G06F13/36

Abstract: Expanded function datagrams in a system power management interface (SPMI) system allow a slave to use an expanded function datagram to address a larger number of masters (e.g., more than four) associated with the SPMI system. Furthermore, addressing may allow for a datagram to be broadcast to multiple masters concurrently. Still further, by signaling that the master addressing is other than the standard SPMI format, the nature of the address and payload of a datagram may be varied to handle larger volumes of data than the SPMI standard normally allows.

公开(公告)号：US11320855B1

公开(公告)日：2022-05-03

申请号：US17131909

申请日：2020-12-23

Applicant: QUALCOMM INCORPORATED

Inventor： Naveen Kumar Narala ,  Matthew Severson

IPC: G06F1/12

Abstract: Debug time stamp counters in a computing device may be synchronized based on signals indicating awakening of a component of the computing device from a sleep state. A count from a global counter in a first component may be loaded into a replica global counter in a second component. The count from the global counter may be loaded into a first debug time stamp counter in the first component in response to a first preload signal indicating awakening of the first component from a sleep state or in response to a second preload signal indicating awakening of the second component from a sleep state. The count from the replica global counter may be loaded into a second debug time stamp counter in the second component in response to the second preload signal.