公开(公告)号：US20240241853A1

公开(公告)日：2024-07-18

申请号：US18155499

申请日：2023-01-17

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Umesh SRIKANTIAH ,  Francesco GATTA ,  Richard Dominic WIETFELDT

IPC: G06F13/42 ,  G06F13/24

CPC classification number: G06F13/4295 ,  G06F13/24

Abstract: A data communication apparatus comprises a line driver configured to couple the data communication apparatus to a 1-wire serial bus; and a controller configured to: transmit a plurality of synchronization pulses over the 1-wire serial bus after a sequence start condition (SSC) has been transmitted over the 1-wire serial bus, the plurality of synchronization pulses being configured to synchronize one or more receiving devices coupled to the 1-wire serial bus to an untransmitted transmit clock signal; initiate an interrupt handling procedure when the plurality of synchronization pulses is encoded with a first value; and initiate a read transaction or a write transaction with at least one of the one or more receiving devices coupled to the 1-wire serial bus when the plurality of synchronization pulses is encoded with a second value.

公开(公告)号：US20240089195A1

公开(公告)日：2024-03-14

申请号：US17943565

申请日：2022-09-13

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Umesh SRIKANTIAH ,  Richard Dominic WIETFELDT ,  Radu PITIGOI-ARON

IPC: H04L45/24

CPC classification number: H04L45/245 ,  H04L12/40

Abstract: A multi-port data communication apparatus includes a first port having a first physical interface circuit configured to couple the multi-port data communication apparatus to a first serial bus that has a first line and a second line, a second port having a second physical interface circuit configured to couple the multi-port data communication apparatus to a second serial bus that has a first line and a second line, and a controller. The controller is configured to use the first port during a first transaction restricted to transmissions over the first serial bus and use the first port and the second port in a second transaction in which data is transmitted over the second line of the first serial bus and the second line of the second serial bus in accordance with timing provided by a clock signal transmitted over the first line of the first serial bus.

公开(公告)号：US20240012778A1

公开(公告)日：2024-01-11

申请号：US17861886

申请日：2022-07-11

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Umesh SRIKANTIAH ,  Francesco GATTA ,  Muhlis Kenan OZEL ,  Richard Dominic WIETFELDT

IPC: G06F13/40 ,  H04L7/00 ,  H04L7/04

CPC classification number: G06F13/4068 ,  H04L7/0066 ,  H04L7/042 ,  H04L7/0087 ,  G06F2213/40

Abstract: A receive clock generated at a receiver coupled to a one-wire bus is synchronized in each clock cycle, permitting reception of a data frame of unlimited length without clock overrun or underrun. A base clock signal provided by an oscillator is passed by a clock gating circuit while the clock gating circuit is enabled. A counter counts positive and negative edges in an output of the clock gating circuit. The clock gating circuit is disabled when an output of the counter indicates a preconfigured maximum count value. An edge synchronization circuit that synchronizes edges in the base clock signal with edges in a data signal received over the one-wire bus ignores edges in the data signal while the counter output has a value that is less than the maximum count value, and resets the counter in response to an edge detected in the data signal received over the one-wire bus.

公开(公告)号：US20220358079A1

公开(公告)日：2022-11-10

申请号：US17307842

申请日：2021-05-04

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Radu PITIGOI-ARON ,  Sharon GRAIF ,  Lior AMARILIO ,  Richard Dominic WIETFELDT

IPC: G06F13/42 ,  G06F1/08 ,  G06F13/20

Abstract: Systems, methods, apparatus and techniques are described that provide point-to-point capabilities without the expected increase in input/output pad usage. In some examples, point-to-point data lines are provided between a host and multiple slave devices and timing of communication is controlled using a clock signal shared by the multiple slave devices. An apparatus has a plurality of bus master circuits configured to control point-to-point communication with corresponding slave devices and a clock generation circuit configured to provide pulses in a serial bus clock signal when one or more bus master circuits are in an active state, and further to idle the serial bus clock signal when all bus master circuits are idle. Each bus master circuit may be configured to communicate with its corresponding slave device in accordance with the timing provided by the serial bus clock signal that is transmitted over a common clock line to each slave device.

公开(公告)号：US20220107912A1

公开(公告)日：2022-04-07

申请号：US17061357

申请日：2020-10-01

Applicant: QUALCOMM Incorporated

Inventor： Richard Dominic WIETFELDT ,  Lalan Jee MISHRA ,  Radu PITIGOI-ARON

IPC: G06F13/42

Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals and control messages over a serial communication link. An apparatus includes a serial bus, and a controller configured to represent a series of signaling state of physical general-purpose input/output (GPIO) in a batch that comprises a sequence of virtual GPIO messages and control messages, generate a first header that includes timing information configured to control timing of execution of the batch, transmit the first header over a communication link, and transmit the batch over the communication link.

公开(公告)号：US20220083483A1

公开(公告)日：2022-03-17

申请号：US17024258

申请日：2020-09-17

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Mohit Kishore PRASAD ,  Richard Dominic WIETFELDT ,  Irfan KHAN

IPC: G06F13/20 ,  G06F13/42

Abstract: Systems, methods, and apparatus for multi-drop coexistence management are described. A data communication apparatus has a bus interface that couples the data communication apparatus to a serial bus and a controller configured to determine that a datagram received from the serial bus is addressed to a register address corresponding to a coexistence management identifier, activate a line driver of the bus interface circuit that is coupled to a data line of the serial bus during a portion of a first payload of the datagram when one or more coexistence management messages are ready for sending from the slave device, where the portion of the first payload of the datagram is allocated for use of the apparatus, and transmit a first coexistence management message in the portion of the first payload of the datagram that is allocated for use of the data communication apparatus.

公开(公告)号：US20200073847A1

公开(公告)日：2020-03-05

申请号：US16678827

申请日：2019-11-08

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Mohit Kishore PRASAD ,  Richard Dominic WIETFELDT ,  Christopher Kong Yee CHUN

IPC: G06F13/42 ,  G06F13/10 ,  G06F13/16 ,  G06F13/20

Abstract: Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A transmitting device generates an address field in a datagram, sets a value of at least one bit in the address field to indicate a number of bytes of data associated with a data frame of the datagram, generates the data frame in the datagram, the data frame including the number of bytes of data, and sends the datagram to a receiving device. A receiving device receives a datagram from a transmitting device, decodes an address field of the datagram to detect a number of bytes of data included in a data frame of the datagram based on a value of at least one bit in the address field, and decodes the data frame to recover the detected number of bytes of data.

公开(公告)号：US20200019524A1

公开(公告)日：2020-01-16

申请号：US16036416

申请日：2018-07-16

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT

IPC: G06F13/366 ,  G06F13/16 ,  G06F13/42

Abstract: Systems, methods, and apparatus for improving bus latency are described. A method performed at a device coupled to a serial bus includes using a dynamic identifier in a first transaction conducted over a first serial bus. The dynamic identifier includes unique identifier and variable identifier portions. The device participates in a sequence of bus arbitrations until the slave device gains access to the first serial bus or a second serial bus. The value of the variable identifier portion may be increased after each bus arbitration that does not result in a grant of access to the first serial bus, and cleared after each bus arbitration that results in a grant of access to the first serial bus. A second transaction may be conducted over the first serial bus after gaining access to the first serial bus. The value of the dynamic identifier defines slave device priority for bus arbitrations.

公开(公告)号：US20200004699A1

公开(公告)日：2020-01-02

申请号：US16426825

申请日：2019-05-30

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT ,  Helena Deirdre O'SHEA

IPC: G06F13/16 ,  G06F13/42 ,  G06F11/10

Abstract: Systems, methods, and apparatus for improving latency of a serial bus are described. A method performed at a device coupled to a serial bus includes writing a first data byte received in a first field of a datagram from a serial bus to a first register in the slave device, modifying the address pointer by adding or subtracting a stride value provided in a second field of the datagram to obtain a modified address pointer, and writing a second data byte received in a third field of the datagram to a second register in the slave device. The first register may be located at an address indicated by an address pointer and the second register may be located at an address indicated by the modified address pointer. The first register and the second register may be located at non-contiguous addresses.

公开(公告)号：US20190050366A1

公开(公告)日：2019-02-14

申请号：US16058599

申请日：2018-08-08

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Raghukul TILAK ,  Zhurang ZHAO ,  Elisha ULMER ,  Richard Dominic WIETFELDT ,  Matthew SEVERSON

IPC: G06F13/42 ,  G06F9/448 ,  G06F9/30

Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals over a serial communication link. A method performed at a device coupled to a serial bus includes determining that GPIO state information corresponding to a physical GPIO pin or signal is available in an event register that has a first bit width and includes information identifying one or more devices associated with the event register, and exchanging the GPIO state information with the one or more devices over the serial bus. The GPIO state information may be transmitted over the serial bus in accordance with configuration information stored in the event register. The configuration information may include an address identifying the one or more devices. The configuration information may include addressing information identifying a target register in the one or more devices. The configuration information may include information identifying a mode of communication for transmitting the GPIO state information.