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    DEVICE, EVENT AND MESSAGE PARAMETER ASSOCIATION IN A MULTI-DROP BUS
    1.
    发明申请
    DEVICE, EVENT AND MESSAGE PARAMETER ASSOCIATION IN A MULTI-DROP BUS 审中-公开

    公开(公告)号：US20190050366A1

    公开(公告)日：2019-02-14

    申请号：US16058599

    申请日：2018-08-08

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee MISHRA ,  Raghukul TILAK ,  Zhurang ZHAO ,  Elisha ULMER ,  Richard Dominic WIETFELDT ,  Matthew SEVERSON

    IPC: G06F13/42 ,  G06F9/448 ,  G06F9/30

    Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals over a serial communication link. A method performed at a device coupled to a serial bus includes determining that GPIO state information corresponding to a physical GPIO pin or signal is available in an event register that has a first bit width and includes information identifying one or more devices associated with the event register, and exchanging the GPIO state information with the one or more devices over the serial bus. The GPIO state information may be transmitted over the serial bus in accordance with configuration information stored in the event register. The configuration information may include an address identifying the one or more devices. The configuration information may include addressing information identifying a target register in the one or more devices. The configuration information may include information identifying a mode of communication for transmitting the GPIO state information.

    Extended Power Threshold Management of Power Rails
    2.
    发明公开
    Extended Power Threshold Management of Power Rails 审中-公开

    公开(公告)号：US20240211021A1

    公开(公告)日：2024-06-27

    申请号：US18069537

    申请日：2022-12-21

    Applicant: QUALCOMM Incorporated

    Inventor： Prashanth Kumar KAKKIRENI ,  Matthew SEVERSON ,  Ravi JENKAL ,  Gordon LEE ,  Kevin Bradley CITTERELLE ,  Ronald ALTON ,  Anish MUTTREJA

    IPC: G06F1/3296

    CPC classification number: G06F1/3296

    Abstract: Various embodiments include power management system methods including receiving, at a processor(s), a notification signal triggering the processor(s) to implement power usage mitigation at the processor(s), determining, by the processor(s), a mitigation amount of power rail power by which to mitigate current usage at a power rail based on a use case for the power rail, and implementing power usage mitigation at the processor(s) by the processor(s) sufficient to mitigate power usage at the power rail by the mitigation amount of power rail power. Power usage mitigation may include reducing processor(s) current usage: by a predefined amount; proportional to the amount a power rail current exceeds a power rail current threshold; by the amount of current exceeding a processor current threshold; or by a smallest amount between the amount a power rail current exceeds a power rail current threshold and the processor(s) current exceeds a processor current threshold.

    Power Management for Multiple-Chiplet Systems
    3.
    发明申请
    Power Management for Multiple-Chiplet Systems 有权

    公开(公告)号：US20220413593A1

    公开(公告)日：2022-12-29

    申请号：US17359350

    申请日：2021-06-25

    Applicant: QUALCOMM Incorporated

    Inventor： Prashanth Kumar KAKKIRENI ,  Matthew SEVERSON ,  Kumar Kanti GHOSH ,  Shishir JOSHI

    IPC: G06F1/3296 ,  H04L12/10

    Abstract: Various embodiments may include methods and systems for power management of multiple chiplets within a system-on-a-chip (SoC). Various systems may include a power management integrated circuit (PMIC) configured to supply power to a first chiplet and a second chiplet across a shared power rail. The first chiplet may be configured to obtain first sensory information throughout the first chiplet. The second chiplet may be configured to obtain second sensory information throughout the second chiplet, and may be configured to transmit a voltage change message to the first chiplet based on the second sensory information. The first chiplet may be configured to transmit a power rail adjustment message to the PMIC based on the first sensory information and the voltage change message. The PMIC may be configured to adjust the voltage of at least one of the first chiplet and the second chiplet.

    ENERGY EFFICIENT VMIN ARCHITECTURE FOR SHARED RAILS
    8.
    发明公开
    ENERGY EFFICIENT VMIN ARCHITECTURE FOR SHARED RAILS 审中-公开

    公开(公告)号：US20240264651A1

    公开(公告)日：2024-08-08

    申请号：US18166381

    申请日：2023-02-08

    Applicant: QUALCOMM Incorporated

    Inventor： Vijayakumar Ashok DIBBAD ,  Nikhil Ashok BHELAVE ,  Jeffrey GEMAR ,  Matthew SEVERSON

    IPC: G06F1/30

    CPC classification number: G06F1/305

    Abstract: Various embodiments include methods performed by a processor for managing voltage droop margins of a power distribution network (PDN). Various embodiments may include receiving, by a processor from a first client powered by a shared power rail within the PDN, a first requested performance corner, receiving, by the processor from a second client powered by the shared power rail, a second requested performance corner, determining by the processor a first peak current value based on the first requested performance corner, determining by the processor a second peak current value based on the second requested performance corner, determining by the processor a system voltage droop margin based on the first peak current value, the second peak current value, and an impedance value of the PDN, and adjusting a voltage of the shared power rail based on the system voltage droop margin.

    DATA RE-ENCODING FOR ENERGY-EFFICIENT DATA TRANSFER IN A COMPUTING DEVICE
    10.
    发明申请
    DATA RE-ENCODING FOR ENERGY-EFFICIENT DATA TRANSFER IN A COMPUTING DEVICE 有权

    公开(公告)号：US20230031310A1

    公开(公告)日：2023-02-02

    申请号：US17390215

    申请日：2021-07-30

    Applicant: QUALCOMM INCORPORATED

    Inventor： ENGIN IPEK ,  Bohuslav RYCHLIK ,  George PATSILARAS ,  Prajakt KULKARNI ,  Can HANKENDI ,  Fahad ALI ,  Jeffrey GEMAR ,  Matthew SEVERSON

    IPC: G06F13/16

    Abstract: The energy consumed by data transfer in a computing device may be reduced by transferring data that has been encoded in a manner that reduces the number of one “1” data values, the number of signal level transitions, or both. A data destination component of the computing device may receive data encoded in such a manner from a data source component of the computing device over a data communication interconnect, such as an off-chip interconnect. The data may be encoded using minimum Hamming weight encoding, which reduces the number of one “1” data values. The received data may be decoded using minimum Hamming weight decoding. For other computing devices, the data may be encoded using maximum Hamming weight encoding, which increases the number of one “1” data values while reducing the number of zero “0” values, if reducing the number of zero values reduces energy consumption.

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