公开(公告)号：US20250022858A1

公开(公告)日：2025-01-16

申请号：US18352976

申请日：2023-07-14

Applicant: QUALCOMM Incorporated

Inventor： Kai LIU ,  Jui-Yi CHIU ,  Jonghae KIM ,  Je-Hsiung LAN ,  Nosun PARK

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/522

Abstract: A device comprising (i) a first device portion comprising: a die substrate; at least one first dielectric layer; a first plurality of interconnects; a first encapsulation layer; and a first plurality of via interconnects located at least in the first encapsulation layer; (ii) a second device portion comprising: at least one second dielectric layer; a second plurality of interconnects; a second encapsulation layer; and a second plurality of via interconnects located at least in the second encapsulation layer; and (iii) a first plurality of solder interconnects coupled to the first device portion and the second device portion, wherein the first plurality of interconnects, the first plurality of via interconnects, the first plurality of solder interconnects, the second plurality of interconnects and the second plurality of via interconnects are configured to operate as an inductor.

公开(公告)号：US20240258995A1

公开(公告)日：2024-08-01

申请号：US18160917

申请日：2023-01-27

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung LAN ,  Jonghae KIM ,  Nosun PARK ,  Jui-Yi CHIU ,  Kai LIU

IPC: H03H9/54 ,  H03H3/02 ,  H03H3/08 ,  H03H9/17 ,  H03H9/25 ,  H03H9/64

CPC classification number: H03H9/542 ,  H01L28/40 ,  H03H3/02 ,  H03H3/08 ,  H03H9/171 ,  H03H9/25 ,  H03H9/64

Abstract: A compact, hybrid, acoustic wave filter structure is disclosed. In an aspect an apparatus comprises a substrate; a first, multi-layer metallization structure disposed above the substrate; a plurality of pillar structures disposed above, and electrically coupled to, the first metallization structure; a second metallization structure disposed above, an electrically coupled to, the plurality of pillar structures. An acoustic unit (AU) is disposed between the first and second metallization structures and adjacent to at least one of the pillar structures. The AU comprises a surface acoustic wave or bulk acoustic wave acoustic resonator that is electrically coupled to a capacitor and an inductor. The capacitor comprises a metal-insulation-metal capacitor that is formed from a portion of the first metallization structure and optionally also from at least one pillar structure and a portion of the second metallization structure. The inductor is comprised of a second portion of the first metallization structure.

公开(公告)号：US20240203895A1

公开(公告)日：2024-06-20

申请号：US18067565

申请日：2022-12-16

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung LAN ,  Jonghae KIM ,  Ranadeep DUTTA

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L21/566 ,  H01L21/568 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/0655 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2924/14215 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/2027 ,  H01L2924/3025

Abstract: Disclosed are examples of multi-die modules that includes a die (e.g., a power amplifier) and an adjacent die placed side-by-side and bonded onto a substrate with a mold compound. The die (e.g., a switch or a low noise amplifier) may be double EMI shielded to minimize or even eliminate EMI/noise coupling with the adjacent die (e.g., switch, low noise amplifier, etc.). Another mold compound, which can be thermally conductive, may be provided to improve transfer of heat away from the die and/or the adjacent die.

公开(公告)号：US20230187106A1

公开(公告)日：2023-06-15

申请号：US17643685

申请日：2021-12-10

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Sang-June PARK ,  Je-Hsiung LAN ,  Ranadeep DUTTA

IPC: H01C7/00

CPC classification number: H01C7/006

Abstract: Disclosed is a sheet resistor designed to operate in a high frequency environment. Unlike conventional sheet resistors, the equivalent series inductance (ESL) is minimized or even eliminated altogether when using the designed sheet resistor. As a result, better signal isolation can be achieved.

公开(公告)号：US20220352359A1

公开(公告)日：2022-11-03

申请号：US17244293

申请日：2021-04-29

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep DUTTA ,  Jonghae KIM ,  Je-Hsiung LAN

IPC: H01L29/737 ,  H01L29/205 ,  H01L29/66 ,  H01L23/498 ,  H01L23/14 ,  H01L23/00

Abstract: In an aspect, a heterojunction bipolar transistor (HBT) includes a sub-collector disposed on a collector. The collector has a collector contact disposed on the sub-collector and located on a first side of the heterojunction bipolar transistor. The HBT includes an emitter disposed on an emitter cap. The emitter has an emitter contact disposed on the emitter cap and located on a second side of the heterojunction bipolar transistor. The HBT includes a base having a base contact located on the second side of the heterojunction bipolar transistor.

公开(公告)号：US20220084922A1

公开(公告)日：2022-03-17

申请号：US17323249

申请日：2021-05-18

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung LAN ,  Jonghae KIM ,  Jinseong KIM

IPC: H01L23/498 ,  H01L23/64 ,  H01L21/48

Abstract: An integrated circuit (IC) package includes a chip. The chip has a front-side surface and a backside surface, opposite the front-side surface. The front-side surface of the chip includes a plurality of bump sites. The integrated circuit package also includes a plurality of dies. Each of the plurality of dies are composed of integrated passive devices. The plurality of dies have conformal die edge patterns to enable placement of a front-side surface of each of the plurality of dies on predetermined portions of the plurality of bumps sites on the front-side surface of the chip.

公开(公告)号：US20210376810A1

公开(公告)日：2021-12-02

申请号：US16884891

申请日：2020-05-27

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Je-Hsiung LAN ,  Ranadeep DUTTA ,  Milind SHAH ,  Periannan CHIDAMBARAM

IPC: H03H9/05 ,  H01L41/053 ,  H01L41/047 ,  H03H9/145 ,  H01L25/04 ,  H03H9/64 ,  H01L41/23 ,  H03H3/02 ,  H03H9/02

Abstract: A package that includes a first filter comprising a first polymer, a substrate cap, a second filter comprising a second polymer frame, at least one interconnect, an encapsulation layer and a plurality of through encapsulation vias. The substrate cap is coupled to the first polymer frame such that a first void is formed between the substrate cap and the first filter. The second polymer frame is coupled to the substrate cap such that a second void is formed between the substrate cap and the second filter. The at least one interconnect is coupled to the first filter and the second filter. The encapsulation layer encapsulates the first filter, the substrate cap, the second filter, and the at least one interconnect. The plurality of through encapsulation vias coupled to the first filter.

公开(公告)号：US20210327873A1

公开(公告)日：2021-10-21

申请号：US16854313

申请日：2020-04-21

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung LAN ,  Ranadeep DUTTA ,  Jonghae KIM

IPC: H01L27/06 ,  H03F3/213 ,  H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: A 3D integrated circuit (3D IC) chip is described. The 3D IC chip includes a die having a compound semiconductor high electron mobility transistor (HEMT) active device. The compound semiconductor HEMT active device is composed of compound semiconductor layers on a single crystal, compound semiconductor layer. The 3D IC chip also includes an acoustic device integrated in the single crystal, compound semiconductor layer. The 3D IC chip further includes a passive device integrated in back-end-of-line layers of the die on the single crystal, compound semiconductor layer.

公开(公告)号：US20210104447A1

公开(公告)日：2021-04-08

申请号：US16592471

申请日：2019-10-03

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Je-Hsiung LAN ,  Ranadeep DUTTA

IPC: H01L23/367 ,  H01L27/12 ,  H01L23/552 ,  H01L23/373 ,  H01L23/00 ,  H01L23/48 ,  H01L21/56

Abstract: Active devices in an integrated circuit (IC) die package, such as in a radio frequency front end (RFFE) package can generate significant amount of heat. This problem can become acute especially as the operating frequency is high such as in 5G NR. Also, electromagnetic interference issues can arise in such packages. One or more techniques to mitigate thermal and electrical interference issues in IC die packages are presented.

公开(公告)号：US20150014812A1

公开(公告)日：2015-01-15

申请号：US14149530

申请日：2014-01-07

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung LAN ,  Chengjie ZUO ,  Changhan Hobie YUN ,  Jonghae KIM ,  Daeik Daniel KIM ,  Mario Francisco VELEZ ,  Robert Paul MIKULKA ,  Niranjan Sunil MUDAKATTE

IPC: H01L49/02

CPC classification number: H01L23/49822 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/642 ,  H01L23/645 ,  H01L27/016 ,  H01L27/0805 ,  H01L28/10 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device includes a substrate, and a first interlayer dielectric layer on the substrate that includes a first conductive layer and a second conductive layer. The integrated circuit device also includes a first conductive stack including a third conductive layer coupled to a portion of the second conductive layer with a first via. The integrated circuit device further includes a second conductive stack comprising a fourth conductive layer directly on a portion of the third conductive layer that is isolated from the substrate. The integrated circuit device also includes a second interlayer dielectric layer surrounding the third conductive layer and the fourth conductive layer.

Abstract translation: 集成电路器件包括衬底，以及在衬底上的包括第一导电层和第二导电层的第一层间电介质层。 集成电路器件还包括第一导电叠层，其包括用第一通孔耦合到第二导电层的一部分的第三导电层。 集成电路器件还包括第二导电叠层，其包括直接位于与衬底隔离的第三导电层的一部分上的第四导电层。 集成电路器件还包括围绕第三导电层和第四导电层的第二层间介质层。