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公开(公告)号：US20220414814A1
公开(公告)日：2022-12-29
申请号：US17356434
申请日：2021-06-23
Applicant: QUALCOMM Incorporated
Inventor： Yun DU , Andrew Evan GRUBER , Chihong ZHANG , Jian JIANG , Gang ZHONG , Baoguang YANG , Yang XIA , Chun YU , Eric DEMERS
Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may generate a table including a plurality of entries to store data associated with at least one of a constant value or an immediate value. The apparatus may also process, upon generating the table, first data including at least one of a constant value or an immediate value. Further, the apparatus may store, in the generated table, at least one of the constant value or the immediate value of the first data. The apparatus may also transmit, upon storing at least one of the constant value or the immediate value in the table, the table including the stored at least one of the constant value or the immediate value of the first data.
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公开(公告)号：US20210209717A1
公开(公告)日：2021-07-08
申请号：US16734252
申请日：2020-01-03
Applicant: QUALCOMM INCORPORATED
Inventor： Yun DU , Chun YU , Andrew Evan GRUBER , Zilin YING , Baoguang YANG
Abstract: Methods, systems, and devices for image processing are described. A device may determine, based on a test operation, to terminate a first wave associated with a first slot of a set of slots. The device may update a terminated wave bit associated with the first slot based on the determination to terminate the first wave. In some aspects, the device may update a number of invocations field associated with the first wave based on the determination to terminate the first wave. The device may release the first slot based on updating the terminated wave bit and the number of invocations field. In some examples, the device may output the number of invocations field to a rendering backend of the device based on the terminated wave bit.
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公开(公告)号：US20210200836A1
公开(公告)日：2021-07-01
申请号：US17137226
申请日：2020-12-29
Applicant: QUALCOMM Incorporated
Inventor： Yun DU , Gang ZHONG , Fei WEI , Yibin ZHANG , Jing HAN , Hongjiang SHANG , Elina KAMENETSKAYA , Minjie HUANG , Alexei Vladimirovich BOURD , Chun YU , Andrew Evan GRUBER , Eric DEMERS
Abstract: The present disclosure relates to methods and apparatus for compute processing. For example, disclosed techniques facilitate improving performance of matrix multiplication in streaming processor. Aspects of the present disclosure can execute, with a load control unit, a first load instruction to load a set of input data of an input matrix from a first memory to a second memory. Aspects of the present disclosure can also execute, with the load control unit, a second load instruction to load a set of weight data of a weight matrix from the first memory to the second memory. Additionally, aspects of the present disclosure can perform, with an ALU component, a matrix multiplication operation using the set of input data and the set of weight data to generate an output matrix. Further, aspects of the present disclosure can store the output matrix at a general purpose register accessible to the ALU component.
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公开(公告)号：US20210133912A1
公开(公告)日：2021-05-06
申请号：US16673564
申请日：2019-11-04
Applicant: QUALCOMM Incorporated
Inventor： Tao WANG , Shambhoo KHANDELWAL , Andrew Evan GRUBER , Shangmei YU , Jing GAO , Junmei SHAO , Thomas Edwin Frisinger , Rick Hammerstone
Abstract: The present disclosure relates to methods and apparatus for graphics processing. Aspects of the present disclosure can determine a portion of a display area, where the portion of the display area is determined based on display content of the display area. Further, aspects of the present disclosure can communicate display information corresponding to the determined portion of the display area. Additionally, aspects of the present disclosure can update the display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also communicate the updated display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also render at least some display content of the display area corresponding to the determined portion of the display area. In some aspects, the updated display information can be based on the rendered display content of the display area.
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公开(公告)号：US20200312006A1
公开(公告)日：2020-10-01
申请号：US16364829
申请日：2019-03-26
Applicant: QUALCOMM Incorporated
Inventor： Yun DU , Andrew Evan GRUBER , Chun YU , Chihong ZHANG , Hongjiang SHANG , Zilin YING , Fei WEI
Abstract: Example techniques are described for generating graphics content by obtaining texture operation instructions corresponding to a texture operation, in response to determining at least one of insufficient general purpose register space is available for the texture operation or insufficient wave slots are available for the texture operation, generating an indication that the texture operation corresponds to a deferred wave, executing the texture operation, sending, to a texture processor, initial texture sample instructions corresponding to the texture operation that was executed, and receiving texture mapped data corresponding to the initial texture sample instructions.
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Patent Agency Ranking
公开(公告)号：US20200210299A1
公开(公告)日：2020-07-02
申请号：US16815718
申请日：2020-03-11
Applicant: QUALCOMM Incorporated
Inventor： Rahul GULATI , Andrew Evan GRUBER , Brendon Lewis JOHNSON , Jay Chunsup YUN , Donghyun KIM , Alex Kwang Ho JONG , Anshuman SAXENA
IPC: G06F11/22 , G06T1/20 , G06T15/00 , G06F11/07 , G01R31/317 , G01R31/3187 , G06F11/277
Abstract: The disclosure describes techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.
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公开(公告)号：US20240370967A1
公开(公告)日：2024-11-07
申请号：US18777430
申请日：2024-07-18
Applicant: QUALCOMM Incorporated
Inventor： Kalyan Kumar BHIRAVABHATLA , Andrew Evan GRUBER , Rahul Sunil KUKREJA , Vishwanath Shashikant NIKAM , Tao WANG , Jian LIANG
Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for improving visibility generation in tile-based GPU architectures. A graphics processor may perform a first binning pass associated with visibility information for each of a plurality of primitives in at least one frame. The visibility information for each of the plurality of primitives may correspond to a visible indication or an invisible indication. The graphics processor may update a depth buffer based on the visibility information for all of the plurality of primitives in the at least one frame. The graphics processor may perform a second binning pass for each of the visible set of primitives based on the updated depth buffer. The graphics processor may store at least one of the updated visibility information or updated position data for all primitives in the visible set of primitives from the second binning pass.
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公开(公告)号：US20240104684A1
公开(公告)日：2024-03-28
申请号：US17935031
申请日：2022-09-23
Applicant: QUALCOMM Incorporated
Inventor： Kalyan Kumar BHIRAVABHATLA , Andrew Evan GRUBER , Rahul Sunil KUKREJA , Vishwanath Shashikant NIKAM , Tao WANG , Jian LIANG
Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for improving visibility generation in tile-based GPU architectures. A graphics processor may perform a first binning pass associated with visibility information for each of a plurality of primitives in at least one frame. The visibility information for each of the plurality of primitives may correspond to a visible indication or an invisible indication. The graphics processor may update a depth buffer based on the visibility information for all of the plurality of primitives in the at least one frame. The graphics processor may perform a second binning pass for each of the visible set of primitives based on the updated depth buffer. The graphics processor may store at least one of the updated visibility information or updated position data for all primitives in the visible set of primitives from the second binning pass.
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公开(公告)号：US20240037183A1
公开(公告)日：2024-02-01
申请号：US18487918
申请日：2023-10-16
Applicant: QUALCOMM Incorporated
Inventor： Yun DU , Gang ZHONG , Fei WEI , Yibin ZHANG , Jing HAN , Hongjiang SHANG , Elina KAMENETSKAYA , Minjie HUANG , Alexei Vladimirovich BOURD , Chun YU , Andrew Evan GRUBER , Eric DEMERS
Abstract: The present disclosure relates to methods and apparatus for compute processing. For example, disclosed techniques facilitate improving performance of matrix multiplication in streaming processor. Aspects of the present disclosure can execute, with a load control unit, a first load instruction to load a set of input data of an input matrix from a first memory to a second memory. Aspects of the present disclosure can also execute, with the load control unit, a second load instruction to load a set of weight data of a weight matrix from the first memory to the second memory. Additionally, aspects of the present disclosure can perform, with an ALU component, a matrix multiplication operation using the set of input data and the set of weight data to generate an output matrix. Further, aspects of the present disclosure can store the output matrix at a general purpose register accessible to the ALU component.
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公开(公告)号：US20230394738A1
公开(公告)日：2023-12-07
申请号：US18035507
申请日：2020-11-09
Applicant: QUALCOMM Incorporated
Inventor： Yibin ZHANG , Zilin YING , Yun DU , Heng QI , Jiexia YU , Yang YU , Andrew Evan GRUBER , Jian LIANG , Tao WANG , Alexei Vladimirovich BOURD , Gang ZHONG , Minjie HUANG
IPC: G06T15/00
CPC classification number: G06T15/005
Abstract: The present disclosure relates to methods and apparatus for graphics processing, e.g., a GPU. The apparatus may receive an image including a plurality of pixels associated with one or more workgroups and one or more pixel tiles, each of the workgroups and the pixel tiles including one or more pixels of the plurality of pixels. The apparatus may determine whether the one or more workgroups are misaligned with the one or more pixel tiles. The apparatus may determine a conversion order of the one or more workgroups when the one or more workgroups are misaligned with the one or more pixel tiles, the conversion order corresponding to a common multiple of one of the one or more workgroups and one of the one or more pixel tiles. The apparatus may convert each of the one or more workgroups based on the conversion order of the one or more workgroups.
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