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11.发明申请公开(公告)号：US20190207789A1
公开(公告)日：2019-07-04
申请号：US15857891
申请日：2017-12-29
Applicant: Oracle International Corporation
Inventor： Kunmo Kim , Rajesh Kumar , Dawei Huang , Frankie Liu , Suwen Yang
Abstract: A method and apparatus for correcting baseline wander is disclosed. The method and apparatus may include generating filtered signals by filtering input signals using a filter circuit. An equalizer circuit using the filtered signals may generate output signals. Feedback networks may be configured to couple a respective output signal to a corresponding filtered signal.
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公开(公告)号：US10129121B2
公开(公告)日：2018-11-13
申请号：US15450217
申请日：2017-03-06
Applicant: Oracle International Corporation
Inventor： Philip Kwan , Dawei Huang
Abstract: Embodiments include systems and methods for calibrating clocking circuits for improved jitter performance. Embodiments operate in context of a clocking circuit coupled with a transceiver system that has a receiver that tracks a recovered clock phase according to a tracking code. For example, candidate configurations can be identified, each corresponding to a different respective combination of parameter values for programmable clocking circuit parameters. For each candidate configuration, embodiments can configure the clocking system accordingly, and can sample the tracking code over a sample window to measure a tracking code spread for the candidate configuration. The clocking circuit can be programmed according to which of the candidate configurations manifested a minimum tracking code spread, thereby effectively configuring the clocking circuit for minimum jitter generation and optimizing jitter performance of the transceiver.
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公开(公告)号：US20180278405A1
公开(公告)日：2018-09-27
申请号：US15466469
申请日：2017-03-22
Applicant: Oracle International Corporation
Inventor： Yuhan Yao , Xun Zhang , Dawei Huang , Jianghui Su , Muthukumar Vairavan , Chaitanya Palusa
CPC classification number: H04L7/0008 , H03L7/0807 , H04B1/16 , H04L7/02
Abstract: Embodiments include systems and methods for improving link performance and tracking capability of a baud-rate clock data recovery (CDR) system using transition pattern detection. For example, a multi-level signal is received via a data channel and converted to a pseudo-NRZ signal. CDR early/late voting can be derived from the converted (baud-rate) pseudo-NRZ signal and from error signals from the received PAM4 signal, and the voting can be implemented with different phase error detector (PED) functional approaches. Different approaches can yield different CDR performance characteristics and can tend to favor different PAM4 transition patterns. Embodiments can identify jittery patterns for a particular CDR implementation and can add features to the CDR to filter out those patterns from being used for CDR early/late voting.
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公开(公告)号：US20150015315A1
公开(公告)日：2015-01-15
申请号：US13937424
申请日：2013-07-09
Applicant: Oracle International Corporation
Inventor： Zuxu Qin , Dawei Huang , Deqiang Song , Jianghui Su , Baoqing Huang , Yan Yan
IPC: H03K7/08
CPC classification number: H03K7/08 , H03K5/1565
Abstract: A method and apparatus for duty cycle distortion compensation is disclosed. In one embodiment, an integrated circuit includes a differential signal transmitter having a main data path and a compensation data path. The main data path includes a first and second differential driver circuits each having output terminals coupled to a differential output. A transmission controller is configured to transmit data into the main and compensation data paths, the data corresponding to pairs of sequentially transmitted bits including an odd data bit followed by an even data bit, and further configured to determine respective duty cycle widths for each of the odd and even data bits as received by the transmission controller. The transmission controller is configured to cause the first and second driver circuits to equalize the respective duty cycle widths of the odd and even data bits, as transmitted, based their respective duty cycle widths as received.
Abstract translation: 公开了一种用于占空比失真补偿的方法和装置。 在一个实施例中，集成电路包括具有主数据路径和补偿数据路径的差分信号发送器。 主数据路径包括具有耦合到差分输出的输出端的第一和第二差分驱动器电路。 发送控制器被配置为将数据发送到主和补偿数据路径中，数据对应于顺序发送的比特对，包括奇数数据位，后跟偶数数据位，并进一步被配置为确定各个占空比宽度 由传输控制器接收的奇数和偶数数据位。 传输控制器被配置为使得第一和第二驱动器电路基于其所接收的各自的占空比宽度来均衡发送的奇数和偶数数据位的相应占空比宽度。
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公开(公告)号：US11240073B2
公开(公告)日：2022-02-01
申请号：US16671146
申请日：2019-10-31
Applicant: Oracle International Corporation
Inventor： Xun Zhang , Chaitanya Palusa , Dawei Huang , Muthukumar Vairavan , Jianghui Su
Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, to generate multiple samples for a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.
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Patent Agency Ranking
公开(公告)号：US10778478B2
公开(公告)日：2020-09-15
申请号：US16504958
申请日：2019-07-08
Applicant: Oracle International Corporation
Inventor： Rajesh Kumar , Seno Judaprawira , Dawei Huang
Abstract: A reference generator for use with serial link data communication is disclosed. Broadly speaking, a decision circuit may perform a comparison between a particular data symbol included in a serial data stream and a difference between a voltage level of a first signal and a voltage level of a second signal, and generate an output data value based on a result of the comparison. A reference generator circuit may selectively sink a first current value from either the first signal or the second signal based upon another output data value generated from another data symbol included in the serial data stream that was received prior to the particular data symbol.
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公开(公告)号：US20180254964A1
公开(公告)日：2018-09-06
申请号：US15450217
申请日：2017-03-06
Applicant: Oracle International Corporation
Inventor： Philip Kwan , Dawei Huang
CPC classification number: H04L43/087 , H03L7/0807 , H03L7/0891 , H04B17/14 , H04B17/21
Abstract: Embodiments include systems and methods for calibrating clocking circuits for improved jitter performance. Embodiments operate in context of a clocking circuit coupled with a transceiver system that has a receiver that tracks a recovered clock phase according to a tracking code. For example, candidate configurations can be identified, each corresponding to a different respective combination of parameter values for programmable clocking circuit parameters. For each candidate configuration, embodiments can configure the clocking system accordingly, and can sample the tracking code over a sample window to measure a tracking code spread for the candidate configuration. The clocking circuit can be programmed according to which of the candidate configurations manifested a minimum tracking code spread, thereby effectively configuring the clocking circuit for minimum jitter generation and optimizing jitter performance of the transceiver.
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公开(公告)号：US09306732B2
公开(公告)日：2016-04-05
申请号：US14146605
申请日：2014-01-02
Applicant: Oracle International Corporation
Inventor： Dawei Huang , Jianghui Su , Hongtao Zhang , Deqiang Song
CPC classification number: H04L7/0087 , H04L7/02 , H04L7/0334
Abstract: Embodiments include systems and methods for applying a controllable early/late offset to an at-rate clock data recovery (CDR) system. Some embodiments operate in context of a CDR circuit of a serializer/deserializer (SERDES). For example, slope asymmetry around the first precursor of the channel pulse response for the SERDES can tend to skew at-rate CDR determinations of whether to advance or retard clocking. Accordingly, embodiments use asymmetric voting thresholds for generating each of the advance and retard signals in an attempt to de-skew the voting results and effectively tune the CDR to a position either earlier or later than the first precursor zero crossing (i.e., h(−1)=0) position. This can improve link margin and data recovery, particularly for long data channels and/or at higher data rates.
Abstract translation: 实施例包括将可控早/迟补偿应用于速率时钟数据恢复（CDR）系统的系统和方法。 一些实施例在串行器/解串器（SERDES）的CDR电路的上下文中操作。 例如，针对SERDES的信道脉冲响应的第一前体周围的斜率不对称倾向于偏移速率CDR确定是否提前或延迟时钟。 因此，实施例使用非对称投票阈值来产生提前和延迟信号中的每一个，以试图使投票结果去偏移，并有效地将CDR调谐到比第一前体过零点更早或更晚的位置（即h（ - 1）= 0）位置。 这可以改善链路余量和数据恢复，特别是对于长数据信道和/或更高的数据速率。
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公开(公告)号：US20230155867A1
公开(公告)日：2023-05-18
申请号：US18154248
申请日：2023-01-13
Applicant: Oracle International Corporation
Inventor： Xun Zhang , Chaitanya Palusa , Dawei Huang , Muthukumar Vairavan , Jianghui Su
CPC classification number: H04L25/03057 , H04B1/16
Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.
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公开(公告)号：US20210135907A1
公开(公告)日：2021-05-06
申请号：US16671146
申请日：2019-10-31
Applicant: Oracle International Corporation
Inventor： Xun Zhang , Chaitanya Palusa , Dawei Huang , Muthukumar Vairavan , Jianghui Su
Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, to generate multiple samples for a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.
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