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公开(公告)号：US09996145B2
公开(公告)日：2018-06-12
申请号：US14083398
申请日：2013-11-18
Applicant: NXP B.V.
CPC classification number: G06F1/3296 , G06F1/3243 , G06F13/24 , Y02D10/152 , Y02D10/172
Abstract: A multicore architecture is configured to exploit explicit task parallelism to save power by sharing interrupt sources that trigger independent tasks.
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公开(公告)号：US20150143141A1
公开(公告)日：2015-05-21
申请号：US14083398
申请日：2013-11-18
Applicant: NXP B.V.
CPC classification number: G06F1/3296 , G06F1/3243 , G06F13/24 , Y02D10/152 , Y02D10/172
Abstract: A multicore architecture is configured to exploit explicit task parallelism to save power by sharing interrupt sources that trigger independent tasks.
Abstract translation: 多核体系结构被配置为利用显式任务并行来通过共享引发独立任务的中断源来节省功耗。
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公开(公告)号：US10739846B2
公开(公告)日：2020-08-11
申请号：US16215780
申请日：2018-12-11
Applicant: NXP B.V.
Inventor： Ajay Kapoor , Juan Diego Echeverri Escobar , Kristof Blutman , Sebastien Antonius Josephus Fabrie , Jose de Jesus Pineda de Gyvez , Hamed Fatemi
IPC: H03L5/00 , G06F1/3296 , H03K3/03
Abstract: An electronic device includes a digital circuit, a power delivery subsystem configured to provide a supply voltage and a body-biasing voltage to the digital circuit, and a controller a controller coupled to the power delivery subsystem. The controller is configured to determine a process parameter for the electronic device, determine a current temperature parameter for the electronic device, concurrently determine a first coarse-grain level for the supply voltage and a second coarse-grain level for the body-biasing voltage based on the process parameter, the current temperature parameter, and a frequency of a clock signal to be supplied to the digital circuit, and to determine a fine-grain level for the supply voltage.
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公开(公告)号：US10732698B2
公开(公告)日：2020-08-04
申请号：US15813861
申请日：2017-11-15
Applicant: NXP B.V.
Inventor： Jose de Jesus Pineda de Gyvez , Hamed Fatemi , Manuele Rusci , Luca Benini , Elisabetta Farella , Davide Rossi
IPC: G06F1/32 , G06F1/324 , G06F11/34 , G06F9/48 , G06F1/3228 , G06F1/329 , G06F1/3234
Abstract: A technique for managing power in an embedded processing system includes generating a workload model for the embedded processing system in response to a control signal, an event status signal, and a reference clock signal. The control signal is received from a peripheral device. The event status signal is received from an event processor configured to control execution of tasks by a processor core of the embedded processing system. The technique includes providing power configuration information to the processor core. The power configuration information corresponds to an operating point selected based on the control signal, the event status signal, the reference clock signal, the workload model, and a predetermined energy model.
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公开(公告)号：US09960670B2
公开(公告)日：2018-05-01
申请号：US15052509
申请日：2016-03-11
Applicant: NXP B.V.
Inventor： Ajay Kapoor , Kristóf László Blutman , Jose de Jesus Pineda de Gyvez , Hamed Fatemi
CPC classification number: H02M3/04 , G06F1/26 , H02J1/08 , H02J2001/008 , H02M3/33523 , H02M3/33561
Abstract: One example discloses an apparatus for charge recycling between a first power-domain operating at a first voltage and a second power-domain operating at a second voltage, including: a first power-delivery circuit configured to supply the first voltage to the first power-domain; and a second power-delivery circuit coupled to receive power from both the first power-delivery circuit and the first power-domain; wherein the second power-delivery circuit is configured to supply the second voltage to the second power-domain.
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Patent Agency Ranking
公开(公告)号：US09678564B2
公开(公告)日：2017-06-13
申请号：US13725698
申请日：2012-12-21
Applicant: NXP B.V.
IPC: G06F13/20 , G06F1/32 , G06F13/24 , G06F13/364
CPC classification number: G06F1/329 , G06F13/24 , G06F13/364 , Y02D10/24
Abstract: An intelligent interrupt distributor balances interrupts (workload) in a highly parallelized system. The intelligent interrupt distributor distributes the interrupts between the processor cores. This allows lowering of voltage and frequency of individual processors and ensures that the overall system power consumption is reduced.
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公开(公告)号：US20170012611A1
公开(公告)日：2017-01-12
申请号：US14792276
申请日：2015-07-06
Applicant: NXP B.V.
Inventor： Juan Echeverri Escobar , Jose de Jesus Pineda de Gyvez , Sebastien Antonius Josephus Fabrie
IPC: H03K3/037
CPC classification number: H03K3/0372 , H03K3/012 , H03K3/037 , H03K19/0016
Abstract: Embodiments of a device and method are disclosed. In an embodiment, a flip-flop circuit is disclosed. The flip-flop circuit includes a master latch, a slave latch connected to the master latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling.
Abstract translation: 公开了一种装置和方法的实施例。 在一个实施例中，公开了一种触发器电路。 触发器电路包括主锁存器，连接到主锁存器的从锁存器以及连接在主锁存器和从锁存器之间并被配置为执行状态保持和双重采样的双功能电路。
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公开(公告)号：US20140181351A1
公开(公告)日：2014-06-26
申请号：US13725698
申请日：2012-12-21
Applicant: NXP B.V.
IPC: G06F13/40
CPC classification number: G06F1/329 , G06F13/24 , G06F13/364 , Y02D10/24
Abstract: An intelligent interrupt distributor balances interrupts (workload) in a highly parallelized system. The intelligent interrupt distributor distributes the interrupts between the processor cores. This allows lowering of voltage and frequency of individual processors and ensures that the overall system power consumption is reduced.
Abstract translation: 智能中断分配器平衡高并行化系统中的中断（工作负载）。 智能中断分配器在处理器内核之间分配中断。 这允许降低单个处理器的电压和频率，并确保降低整个系统功耗。
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公开(公告)号：US10942748B2
公开(公告)日：2021-03-09
申请号：US14800952
申请日：2015-07-16
Applicant: NXP B.V.
Abstract: In an embodiment, a method for processing instructions in a microcontroller is disclosed. In the embodiment, the method involves, upon receipt of an interrupt while an instruction is being executed, completing execution of the instruction by a shadow functional unit and, upon servicing the interrupt, terminating re-execution of the instruction and updating a main register file with the result of the execution of the instruction by the shadow functional unit.
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公开(公告)号：US20200183486A1
公开(公告)日：2020-06-11
申请号：US16215780
申请日：2018-12-11
Applicant: NXP B.V.
Inventor： Ajay Kapoor , Juan Diego Echeverri Escobar , Kristof Blutman , Sebastien Antonius Josephus Fabrie , Jose de Jesus Pineda de Gyvez , Hamed Fatemi
IPC: G06F1/3296 , H03K3/03
Abstract: An electronic device includes a digital circuit, a power delivery subsystem configured to provide a supply voltage and a body-biasing voltage to the digital circuit, and a controller a controller coupled to the power delivery subsystem. The controller is configured to determine a process parameter for the electronic device, determine a current temperature parameter for the electronic device, concurrently determine a first coarse-grain level for the supply voltage and a second coarse-grain level for the body-biasing voltage based on the process parameter, the current temperature parameter, and a frequency of a clock signal to be supplied to the digital circuit, and to determine a fine-grain level for the supply voltage.
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