公开(公告)号：US09136841B2

公开(公告)日：2015-09-15

申请号：US13561076

申请日：2012-07-29

Applicant: Kun-Chih Lin ,  Wen-Chi Wu

Inventor： Kun-Chih Lin ,  Wen-Chi Wu

IPC: G01R27/26 ,  H03K17/96 ,  G01D5/24

CPC classification number: H03K17/962 ,  G01D5/24 ,  H03K2217/96074 ,  H03K2217/960745

Abstract: A capacitance difference detecting circuit with a control circuit, a first capacitor, a second capacitor, a voltage control unit and a computing device. The control circuit generates a control signal according to a first voltage and a second voltage. The voltage control unit cooperates with the first capacitor to be detected and the second capacitor to be detected, according to the control signal, to generate the first voltage and the second voltage. The computing device computes a capacitance difference between the first capacitor to be detected and the second capacitor to be detected according to the first voltage, the second voltage and a parameter of the voltage control unit.

Abstract translation: 一种具有控制电路，第一电容器，第二电容器，电压控制单元和计算装置的电容差检测电路。 控制电路根据第一电压和第二电压产生控制信号。 电压控制单元根据控制信号与要检测的第一电容器和待检测的第二电容器协作以产生第一电压和第二电压。 计算装置根据第一电压，第二电压和电压控制单元的参数来计算待检测的第一电容器和待检测的第二电容器之间的电容差。

公开(公告)号：US20120286812A1

公开(公告)日：2012-11-15

申请号：US13561076

申请日：2012-07-29

Applicant: Kun-Chih Lin ,  Wen-Chi Wu

Inventor： Kun-Chih Lin ,  Wen-Chi Wu

IPC: G01R27/26

CPC classification number: H03K17/962 ,  G01D5/24 ,  H03K2217/96074 ,  H03K2217/960745

Abstract: A capacitance difference detecting circuit, which comprises: a control circuit, for generating a control signal according to a first voltage and a second voltage; a first capacitor to be detected; a second capacitor to be detected; a voltage control unit, for cooperating with the first capacitor to be detected and the second capacitor to be detected, according to the control signal, to generate the first voltage and the second voltage; and a computing device, for computing a capacitance difference between the first capacitor to be detected and the second capacitor to be detected according to the first voltage, the second voltage and a parameter of the voltage control unit.

Abstract translation: 一种电容差检测电路，包括：控制电路，用于根据第一电压和第二电压产生控制信号; 要检测的第一电容器; 要检测的第二电容器; 根据控制信号，与要检测的第一电容器和待检测的第二电容器配合的电压控制单元，以产生第一电压和第二电压; 以及计算装置，用于根据第一电压，第二电压和电压控制单元的参数来计算要检测的第一电容器和待检测的第二电容器之间的电容差。

公开(公告)号：US20120227782A1

公开(公告)日：2012-09-13

申请号：US13046471

申请日：2011-03-11

Applicant: Chin-Yao Tsai ,  Yu-Chun Peng ,  Po-Han Lin ,  Yi-Kai Lin ,  Chen-Liang Liao ,  Chih-Hsiung Chang ,  Kun-Chih Lin

Inventor： Chin-Yao Tsai ,  Yu-Chun Peng ,  Po-Han Lin ,  Yi-Kai Lin ,  Chen-Liang Liao ,  Chih-Hsiung Chang ,  Kun-Chih Lin

IPC: H01L31/05

CPC classification number: H01L31/05 ,  H01L31/0201 ,  H01L31/046 ,  Y02E10/50

Abstract: In one aspect of the present invention, a photovoltaic module includes a plurality of sub-modules. Each sub-module includes a plurality of photovoltaic cells spatially arranged as an array, each cell having first and second conductive layers sandwiching an active layer therebetween. The cells in each sub-module are electrically connected to each other in series. Each sub-module further includes positive and negative electrodes formed on the second conductive layers of the first and last cells, respectively, in a respective sub-module. The positive electrode of each sub-module is electrically connected to each other and the negative electrode of each sub-module is electrically connected to each other such that the plurality of sub-modules is electrically connected in parallel. The plurality of sub-modules is spatially arranged next to each other as an array such that at least one sub-module is spatially separated from its immediately next sub-module by a gap.

Abstract translation: 在本发明的一个方面，光伏组件包括多个子模块。 每个子模块包括空间上排列成阵列的多个光伏电池，每个电池具有夹在其间的活性层的第一和第二导电层。 每个子模块中的单元彼此串联电连接。 每个子模块还包括在相应的子模块中分别形成在第一和最后单元的第二导电层上的正极和负极。 每个子模块的正电极彼此电连接，并且每个子模块的负电极彼此电连接，使得多个子模块并联电连接。 多个子模块在空间上彼此相邻布置为阵列，使得至少一个子模块与其紧邻的下一个子模块在空间上与间隙分离。

公开(公告)号：US20110115502A1

公开(公告)日：2011-05-19

申请号：US12703732

申请日：2010-02-10

Applicant: Kun-Chih Lin ,  Wen-Chi Wu

Inventor： Kun-Chih Lin ,  Wen-Chi Wu

IPC: G01R27/26

CPC classification number: H03K17/962 ,  G01D5/24 ,  H03K2217/96074 ,  H03K2217/960745

Abstract: A capacitance difference detecting circuit, which comprises: a control circuit, for generating a control signal according to a first voltage and a second voltage; a first capacitor to be detected; a second capacitor to be detected; a first constant capacitor, having a terminal coupled to the first terminal of the first capacitor to be detected and the first input terminal; a second constant capacitor, having a terminal coupled to the first terminal of the second capacitor to be detected and the second input terminal; a voltage control unit, cooperating with the first capacitor to be detected, the second capacitor to be detected, the first constant capacitor and the second constant capacitor to control the first voltage and the second voltage. The voltage control unit is an adjustable capacitor and a capacitance value of the adjustable capacitor is controlled by the control signal.

Abstract translation: 一种电容差检测电路，包括：控制电路，用于根据第一电压和第二电压产生控制信号; 要检测的第一电容器; 要检测的第二电容器; 第一恒定电容器，具有耦合到待检测的第一电容器的第一端子和第一输入端子的端子; 第二恒定电容器，具有耦合到待检测的第二电容器的第一端子的端子和第二输入端子; 与待检测的第一电容器，待检测的第二电容器，第一恒定电容器和第二恒定电容器配合的电压控制单元，以控制第一电压和第二电压。 电压控制单元是可调电容器，可调电容器的电容值由控制信号控制。

公开(公告)号：US07745243B2

公开(公告)日：2010-06-29

申请号：US12416934

申请日：2009-04-02

Applicant: Yu-Cheng Chen ,  Chen-Yueh Li ,  Ching-Sang Chuang ,  Kun-Chih Lin

Inventor： Yu-Cheng Chen ,  Chen-Yueh Li ,  Ching-Sang Chuang ,  Kun-Chih Lin

IPC: H01L21/8232

CPC classification number: G02F1/133555 ,  G02F2001/136231

Abstract: A forming method of the present invention includes forming a first patterned conductive layer, which includes a transparent conductive layer and a metal layer stacked together on a substrate, where the first patterned conductive layer functions as gate lines, gate electrodes, common lines and predetermined transparent pixel electrode structures; and forming a second patterned conductive layer on the substrate. The second patterned conductive layer includes data lines and reflective pixel electrodes, and be directly connected to doping regions, such as source regions/drain regions. According to the forming method of the present invention, pixel structures of a transflective liquid crystal display device can be formed through five mask processes. Therefore, the manufacturing process of the transflective liquid crystal display device is effectively simplified, so the product yield is improved and the cost can be reduced.

Abstract translation: 本发明的形成方法包括形成第一图案化导电层，其包括在基板上堆叠在一起的透明导电层和金属层，其中第一图案化导电层用作栅极线，栅电极，共同线和预定透明 像素电极结构; 以及在所述衬底上形成第二图案化导电层。 第二图案化导电层包括数据线和反射像素电极，并且直接连接到诸如源极区/漏极区的掺杂区。 根据本发明的形成方法，可以通过五个掩模工艺形成半透射型液晶显示装置的像素结构。 因此，有效地简化了半透射型液晶显示装置的制造工艺，从而提高了产品成品率，降低了成本。

公开(公告)号：US20100006847A1

公开(公告)日：2010-01-14

申请号：US12241071

申请日：2008-09-30

Applicant: Chin-Wei Hu ,  Kun-Chih Lin

Inventor： Chin-Wei Hu ,  Kun-Chih Lin

IPC: H01L21/8238 ,  H01L29/786

CPC classification number: H01L27/1288 ,  H01L21/2652 ,  H01L27/1214 ,  H01L29/66757 ,  H01L29/78621

Abstract: A semiconductor device and the method for fabricating the same are disclosed. The fabrication method includes forming a PMOS device and an NMOS device on a substrate, wherein the PMOS device includes a first poly-silicon island, a gate dielectric layer covering the first poly-silicon island, and a first gate on the gate dielectric layer. The method of fabrication the PMOS device includes performing a P-type ion implantation process on the first poly-silicon island to form a plurality of P-type heavily doped regions and a plurality of P-type lightly doped regions. The length of the channel region is substantially less than 3 micron, and the length of at least one of the P-type lightly doped regions substantially is 10%-80% of the length of the channel region. The P-type lightly doped regions are used to improve the short channel effect of the PMOS device.

Abstract translation: 公开了一种半导体器件及其制造方法。 该制造方法包括在衬底上形成PMOS器件和NMOS器件，其中PMOS器件包括第一多晶硅岛，覆盖第一多晶硅岛的栅极电介质层和栅极介电层上的第一栅极。 制造PMOS器件的方法包括在第一多晶硅岛上执行P型离子注入工艺以形成多个P型重掺杂区域和多个P型轻掺杂区域。 沟道区的长度基本上小于3微米，并且P型轻掺杂区中的至少一个的长度基本上是沟道区长度的10％-80％。 P型轻掺杂区域用于改善PMOS器件的短沟道效应。

公开(公告)号：US20090286336A1

公开(公告)日：2009-11-19

申请号：US12426301

申请日：2009-04-20

Applicant: An-Thung Cho ,  Chia-Tien Peng ,  Yuan-Jun Hsu ,  Ching-Chieh Shih ,  Chien-Sen Weng ,  Kun-Chih Lin ,  Hang-Wei Tseug ,  Ming-Huang Chuang

Inventor： An-Thung Cho ,  Chia-Tien Peng ,  Yuan-Jun Hsu ,  Ching-Chieh Shih ,  Chien-Sen Weng ,  Kun-Chih Lin ,  Hang-Wei Tseug ,  Ming-Huang Chuang

IPC: H01L21/28

CPC classification number: H01L27/1214 ,  G02F1/13318 ,  G02F1/136213 ,  G02F2201/58 ,  G09G3/3406 ,  G09G3/3611 ,  G09G2320/0626 ,  G09G2320/066 ,  G09G2330/021 ,  G09G2360/144 ,  H01L27/127 ,  H01L31/103 ,  H01L31/105 ,  H04N5/58 ,  H04N5/66 ,  H04N21/42202

Abstract: A manufacturing method of a thin film transistor array substrate incorporating the manufacture of a photo-sensor is provided. In the manufacturing method, a photo-sensing dielectric layer is formed between a transparent conductive layer and a metal electrode for detecting ambient light. Since the transparent conductive layer is adopted as an electrode, the ambient light can pass through the transparent conductive layer and get incident light into the photo-sensing dielectric layer. Therefore, the sensing area of the photo-sensor can be enlarged and the photo-sensing efficiency is improved. In addition, the other side of the photo sensitive dielectric layer may be a metal electrode. The metal electrode can block the backlight from getting incident into the photo-sensing dielectric layer and thus reduce the background noise. A manufacturing method of a liquid crystal display panel adopting the aforementioned thin film transistor array substrate is also provided.

Abstract translation: 提供了结合光传感器的制造的薄膜晶体管阵列基板的制造方法。 在制造方法中，在透明导电层和用于检测环境光的金属电极之间形成感光电介质层。 由于采用透明导电层作为电极，所以环境光可以通过透明导电层，并将入射光入射到感光电介质层中。 因此，可以扩大光传感器的感测面积，提高感光效率。 此外，光敏电介质层的另一侧可以是金属电极。 金属电极可阻挡背光入射到感光电介质层中，从而降低背景噪声。 还提供了采用上述薄膜晶体管阵列基板的液晶显示面板的制造方法。

公开(公告)号：US20080296581A1

公开(公告)日：2008-12-04

申请号：US11892191

申请日：2007-08-21

Applicant: Chih-Wei Chao ,  Yi-Sheng Cheng ,  Kun-Chih Lin ,  Yi-Wei Chen

Inventor： Chih-Wei Chao ,  Yi-Sheng Cheng ,  Kun-Chih Lin ,  Yi-Wei Chen

IPC: H01L21/00 ,  H01L29/786

CPC classification number: H01L27/1248 ,  G02F1/136213 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/78621

Abstract: A pixel structure including at least one thin-film transistor, at least one storage capacitor, a patterned first metal layer, an interlayer dielectric layer, a passivation layer, and a patterned pixel electrode is provided. The storage capacitor is electrically connected to the thin-film transistor. The patterned first metal layer is covered by the interlayer dielectric layer. The thin-film transistor and the interlayer dielectric layer are covered by the passivation layer, wherein an opening is formed in the passivation layer and a part of the interlayer dielectric layer. The patterned pixel electrode is formed on a part of the passivation layer and a part of the interlayer dielectric layer and contacted with a part of the passivation layer and a part of the interlayer dielectric layer. The storage capacitor includes the patterned first metal layer, a remained part of the interlayer dielectric layer located under the opening, and the patterned pixel electrode.

Abstract translation: 提供了包括至少一个薄膜晶体管，至少一个存储电容器，图案化第一金属层，层间介电层，钝化层和图案化像素电极的像素结构。 存储电容器电连接到薄膜晶体管。 图案化的第一金属层被层间介电层覆盖。 薄膜晶体管和层间电介质层被钝化层覆盖，其中在钝化层中形成一个开口和一部分层间电介质层。 图案化的像素电极形成在钝化层的一部分和层间电介质层的一部分上，并与钝化层的一部分和层间电介质层的一部分接触。 存储电容器包括图案化的第一金属层，位于开口下方的层间介电层的剩余部分和图案化的像素电极。

公开(公告)号：US08361818B2

公开(公告)日：2013-01-29

申请号：US12874203

申请日：2010-09-01

Applicant: An-Thung Cho ,  Chia-Tien Peng ,  Kun-Chih Lin

Inventor： An-Thung Cho ,  Chia-Tien Peng ,  Kun-Chih Lin

IPC: H01L21/00

CPC classification number: H01L31/0384 ,  H01L27/14667 ,  H01L27/14692 ,  H01L31/03921 ,  Y02E10/50

Abstract: A method of forming an optical sensor includes the following steps. A substrate is provided, and a read-out device is formed on the substrate. a first electrode electrically connected to the read-out device is formed on the substrate. a photosensitive silicon-rich dielectric layer is formed on the first electrode, wherein the photosensitive silicon-rich dielectric layer comprises a plurality of nanocrystalline silicon crystals. A second electrode is formed on the photosensitive silicon-rich dielectric layer.

Abstract translation: 形成光学传感器的方法包括以下步骤。 提供基板，并且在基板上形成读出装置。 电连接到读出装置的第一电极形成在基板上。 在第一电极上形成感光性富硅介电层，其中感光性富硅介电层包含多个纳米晶体硅晶体。 第二电极形成在感光富硅电介质层上。

公开(公告)号：US08232978B2

公开(公告)日：2012-07-31

申请号：US12465666

申请日：2009-05-14

Applicant: Wen-Jen Chiang ,  An-Thung Cho ,  Chrong-Jung Lin ,  Chia-Tien Peng ,  Ya-Chin King ,  Kun-Chih Lin ,  Chih-Wei Chao ,  Chien-Sen Weng ,  Feng-Yuan Gan

Inventor： Wen-Jen Chiang ,  An-Thung Cho ,  Chrong-Jung Lin ,  Chia-Tien Peng ,  Ya-Chin King ,  Kun-Chih Lin ,  Chih-Wei Chao ,  Chien-Sen Weng ,  Feng-Yuan Gan

IPC: G06F3/042 ,  G06G3/36 ,  G09G5/00

CPC classification number: G06F3/0412 ,  G06F3/0421

Abstract: An optical reflective touch panel and pixels and a system thereof are provided. Each pixel of the optical reflective touch panel includes a display circuit and a sensing circuit. The display circuit controls the display of the pixel. The sensing circuit is coupled to the display circuit for sensing a sensitization state of the pixel during a turned-on period and a turned-off period of a backlight module and outputting a digital signal to notify an optical reflective touch panel system that whether the pixel is touched or not.

Abstract translation: 提供光反射式触摸面板及其像素及其系统。 光反射式触摸面板的每个像素包括显示电路和感测电路。 显示电路控制像素的显示。 感测电路耦合到显示电路，用于在背光模块的导通周期和关闭周期期间感测像素的感光状态，并输出数字信号以通知光反射式触摸面板系统，该像素是否是像素 是否被触动